MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 507

• Manufacturer Part Number: MPC562MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC562MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

generated internally and the QADC64E immediately begins execution of the first CCW in the queue. If a
pause occurs, another trigger event is generated internally, and then execution continues without pausing.
The QADC64E automatically performs the conversions in the queue until an end-of-queue condition is
encountered. The queue remains idle until the software again sets the single-scan enable bit. While the time
to internally generate and act on a trigger event is very short, software can momentarily read the status
conditions, indicating that the queue is paused. The trigger overrun flag is never set while in the software
initiated single-scan mode.
The software initiated single-scan mode is useful in the following applications:
13.5.4.3.2
The external trigger single-scan mode is available on both queue 1 and queue 2. The software programs
the polarity of the external trigger edge that is to be detected, either a rising or a falling edge. The software
must enable the scan to occur by setting the single-scan enable bit for the queue.
The first external trigger edge causes the queue to be executed one time. Each CCW is read and the
indicated conversions are performed until an end-of-queue condition is encountered. After the queue is
completed, the QADC64E clears the single-scan enable bit. Software may set the single-scan enable bit
again to allow another scan of the queue to be initiated by the next external trigger edge.
The external trigger single-scan mode is useful when the input trigger rate can exceed the queue execution
rate. Analog samples can be taken in sync with an external event, even though the software is not interested
in data taken from every edge. The software can start the external trigger single-scan mode and get one set
of data, and at a later time, start the queue again for the next set of samples.
When a pause bit is encountered during external trigger single-scan mode, another trigger event is required
for queue execution to continue. Software involvement is not needed to enable queue execution to continue
from the paused state.
13.5.4.3.3
The QADC64E provides external gating for queue 1 only. When external gated single-scan mode is
selected, the input level on the associated external trigger signal enables and disables queue execution. The
polarity of the external gated signal is fixed so only a high level opens the gate and a low level closes the
gate. Once the gate is open, each CCW is read and the indicated conversions are performed until the gate
is closed. Software must enable the scan to occur by setting the single-scan enable bit for queue 1. If a
pause in a CCW is encountered, the pause flag will not set, and execution continues without pausing.
While the gate is open, queue 1 executes one time. Each CCW is read and the indicated conversions are
performed until an end-of-queue condition is encountered. When queue 1 completes, the QADC64E sets
the completion flag (CF1) and clears the single-scan enable bit. Software may set the single-scan enable
bit again to allow another scan of queue 1 to be initiated during the next open gate.
If the gate closes before queue 1 completes execution, the current CCW completes, execution of queue 1
stops, the single-scan enable bit is cleared, and the PF1 bit is set. Software can read the CWPQ1 to
Freescale Semiconductor
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Allows software complete control of the queue execution
Allows the software to easily alternate between several queue sequences.
External Trigger Single-Scan Mode
External Gated Single-Scan Mode
MPC561/MPC563 Reference Manual, Rev. 1.2
QADC64E Legacy Mode Operation
13-43