MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 470

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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QADC64E Legacy Mode Operation
channel field of the conversion command word (CCW) table. External Multiplex mode is software
selectable, by setting the EMUX bit of control register 0, QACR0.
Figure 13-3
The QADC provides three multiplexer address signals – MA[0], MA[1], MA[2] – to select one of the
multiplexer chips. These outputs are the multiplexer control lines and they are connected to all external
multiplexer chips.
The analog output of each of the four multiplexer chips is connected to four separate QADC inputs – ANw,
ANx, ANy, ANz. These signals are the first four signals of port B and each one can represent eight analog
input channels. The QADC converts the proper input channel (ANw, ANx, ANy, ANz) by interpreting the
channel number in the CCW. Refer to
In the external multiplexed mode, four of the port B signals are redefined to each represent eight input
channels. Refer to
13-6
AN[10]
AN[12]
AN[14]
AN[13]
AN[15]
AN[16]
AN[18]
AN[20]
AN[22]
AN[24]
AN[26]
AN[28]
AN[30]
AN[17]
AN[19]
AN[21]
AN[23]
AN[25]
AN[27]
AN[29]
AN[31]
AN[11]
AN[0]
AN[2]
AN[4]
AN[6]
AN[8]
AN[1]
AN[3]
AN[5]
AN[7]
AN[9]
shows the maximum configuration of four external multiplexer chips connected to the QADC.
MUX
MUX
MUX
MUX
Table 13-3
External Triggers:
ETRIG1
ETRIG2
Figure 13-3. Example of External Multiplexing
for more information.
AN[52]/MA[0]/PQA[0]
AN[53]/MA[1]/PQA[1]
AN[54]/MA[2]/PQA[2]
AN[0]/ANw/PQB[0]
AN[2]/ANy/PQB[2
AN[3]/ANz/PQB[3]
AN[1]/ANx/PQB[1
MPC561/MPC563 Reference Manual, Rev. 1.2
AN[48]/PQB[4]
AN[49]/PQB[5]
AN[50]/PQB[6]
AN[51]/PQB[7]
AN[55]/PQA[3]
AN[56]/PQA[4]
AN[58]/PQA[6]
AN[59]/PQA[7]
AN[57]PQA[5]
Table
V SSA
V DDA
V
V RL
RH
13-3.
]
]
ANALOG REFERENCES
ANALOG POWER
MULTIPLEXER
PORT LOGIC
ANALOG
AND
CONVERTER
ANALOG
QADC
Freescale Semiconductor
DIGITAL
CONTROL

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