MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 460

• Manufacturer Part Number: MPC562MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC562MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

U-Bus to IMB3 Bus Interface (UIMB)
The UIPEND register contains a status bit for each of the 32 interrupt levels. Each bit of the register is a
read-only status bit, reflecting the current state of the corresponding interrupt signal. For each of the 32
interrupt levels, a corresponding bit of the UIPEND register is set.
Figure 12-4
levels of interrupts.
12.5
Table 12-5
in this table is from the start of the block reserved for UIMB registers. As shown in
begins at offset 0x30 7F80 from the start of the MPC561/MPC563 internal memory map (the last 128-byte
sub-block of the UIMB interface memory map).
12-6
IMB3 LVL [0:7]
Access
IMBCLOCK
ILBS [0:1]
—
S
Programming Model
RESET
lists the registers used for configuring and testing the UIMB module. The address offset shown
shows how the eight interrupt lines are connected to the UIPEND register to represent 32
1
Software must poll this register to find out which of the levels 7 to 31 are
asserted.
0x30 7F84 — 0x30 7F8F Reserved
Figure 12-6
Base Address
0x30 7F80
Machine
Figure 12-6. Interrupt Synchronizer Block Diagram
State
shows the implementation of the interrupt synchronizer.
Table 12-5. UIMB Interface Register Map
MPC561/MPC563 Reference Manual, Rev. 1.2
4
UIMB Module Configuration Register (UMCR)
See
Table 12-6
NOTE
for bit descriptions.
LVL [8:31]
UIPEND
Register
LVL[0:7]
Register
LVL7
24
32
U-bus Interrupt Level[0:7]
7
OR
Figure
Freescale Semiconductor
U-bus
Data[0:31]
1-2, this block
8