MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 458

• Manufacturer Part Number: MPC562MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC562MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

U-Bus to IMB3 Bus Interface (UIMB)
It is possible for multiple interrupt sources to assert the same interrupt level. To reduce the latency, it is a
good practice for each interrupt source to assert an interrupt on a level on which no other interrupt source
is mapped.
12.4.2
The IMB3 has 10 lines for interrupt support. Eight lines are for interrupts and two are for interrupt level
byte select (ILBS). These lines will transfer the 32 interrupt levels to the interrupt synchronizer. A diagram
of the interrupt flow is shown in
Latching 32 interrupt levels using eight IMB3 interrupt lines is accomplished with a 4:1 time-multiplexing
scheme. The UIMB drives two signals (ILBS[0:1]) with a multiplexer select code that tells all interrupting
modules on the IMB3 about which group of signals to drive during the next clock. See
12.4.3
The IMB3 interface drives the ILBS signals continuously, incrementing through a code sequence (0b00,
0b01, 0b10, 0b11) once every clock. The UMCR[IRQMUX] bits in the IMB3 module configuration
register select which type of multiplexing the interrupt synchronizer will perform. The IRQMUX field can
select time-multiplexing protocols for 8, 16, 24 or 32 interrupt sources. These protocols would take one,
two, three or four clocks, respectively.
Table 12-4
this case the ILBS lines remain at 0b00 at all times. In this mode, no interrupts from IMB3 modules which
assert on levels 8 through 31 are ever latched by the interrupt synchronizer. SRESET will not clear the
IRQMUX bits, so time multiplexing will be enabled with the previous setup after SRESET is released.
The timing for the scheme and the values of ILBS and the interrupt levels driven onto the IMB3 IRQ lines
are shown in
of two clocks before the interrupt request can reach the interrupt synchronizer.
12-4
Byte-enable
to IMB3
shows ILBS sequencing. Programming IRQMUX[0:1] to 0b00 disables time multiplexing. In
IMB3 Interrupt Multiplexing
ILBS Sequencing
Figure
2
12-5. This scheme causes a maximum latency of four clocks and an average latency
Byte Count
Block
Figure 12-4. Interrupt Synchronizer Signal Flow
Figure
MPC561/MPC563 Reference Manual, Rev. 1.2
IMB3 Interrupt
Byte-enables
12-4.
4
8
[16:23]
UIPEND
Register
[24:31]
[8:15]
[0:7]
8
U-bus Interrupt
Level[0:7]
U-bus
Data[0:31]
Freescale Semiconductor
Figure
12-5.