MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 436

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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Memory Controller
10-38
10:12
13:31
Bits
1:6
7:9
0
Name
ATM
AM
Reserved
Address mask. The address mask field of each option register provides for masking any of the
corresponding bits in the associated base register. By masking the address bits independently,
external devices of different size address ranges can be used. Any clear bit masks the
corresponding address bit. Any set causes the corresponding address bit to be used in the
comparison with the address signals. Address mask bits can be set or cleared in any order in
the field, allowing a resource to reside in more than one area of the address map. This field
can be read or written at any time.
Reserved
Address type mask. This field can be used to mask certain address type bits, allowing more
than one address space type to be assigned to a chip select. Any set bit causes the
corresponding address type code bits to be used as part of the address comparison. Any
cleared bit masks the corresponding address type code bit.
To instruct the memory controller to ignore address type codes as part of the address
comparison, clear the ATM bits.
NOTE: Following a system reset, the ATM bits are cleared in DMOR, except the ATM2 bit. This
means that only data accesses are dual mapped. Refer to the address types definition in
Table
Reserved
9-8.
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 10-12. DMOR Bit Descriptions
Description
Freescale Semiconductor

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