MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 389

• Manufacturer Part Number: MPC562MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC562MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

9.5.11.2
Table 9-9
device that is addressed by the initiated transfer.
9.5.12
When an external master takes ownership of the external bus and the MPC561/MPC563 is programmed
for external master mode operation, the external master can access the internal space of the
MPC561/MPC563 (see
master owns the bus, and the direction of most of the bus signals is inverted, relative to its direction when
the MPC561/MPC563 owns the bus.
The external master gets ownership of the bus and asserts TS in order to initiate an external master access.
The access is directed to the internal bus only if the input address matches the internal address space. The
access is terminated with one of the followings outputs: TA, TEA, or RETRY. If the access completes
successfully, the MPC561/MPC563 asserts TA, and the external master can proceed with another external
master access or relinquish the bus. If an address or data error is detected internally, the MPC561/MPC563
asserts TEA for one clock. TEA should be negated before the second rising edge after it is sampled asserted
in order to avoid the detection of an error for the next bus cycle initiated. TEA is an open drain pin, and
the negation timing depends on the attached pull-up. The MPC561/MPC563 asserts the RETRY signal for
one clock in order to retry the external master access.
If the address of the external access does not match the internal memory space, the internal memory
controller can provide the chip-select and control signals for accesses that belong to one of the memory
controller regions. This feature is explained in
Figure 9-35
Freescale Semiconductor
Asserted
Negated
Negated
summarizes how the MPC561/MPC563 recognizes the termination signals provided by the slave
TEA
Bus Operation in External Master Modes
and
Termination Signals Protocol Summary
Figure 9-36
Section 6.1.2, “External Master
Asserted
Negated
TA
illustrate the basic flow of read and write external master accesses.
X
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 9-9. Termination Signals Protocol
Asserted
RETRY
Chapter 10, “Memory
X
X
Modes”). In external master mode, the external
Normal transfer termination
Retry transfer termination
Transfer error termination
Controller.”
Action
External Bus Interface
9-49