MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 382

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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External Bus Interface
9.5.10
Reservation occurs when a master loads data from memory. The memory location must not be overwritten
until the master finishes processing the data and writing the results back to the reserved location. The
MPC561/MPC563 storage reservation protocol supports a multi-level bus structure. For each local bus,
storage reservation is handled by the local reservation logic.
The protocol tries to optimize reservation cancellation such that an MPC500 processor is notified of
storage reservation loss on a remote bus only when it has issued a conditional storeword (stwcx) cycle to
that address. That is, the reservation loss indication comes as part of the stwcx cycle. This method avoids
the need to have very fast storage reservation loss indication signals routed from every remote bus to every
MPC500 master.
The storage reservation protocol makes the following assumptions:
The reservation protocol for a single-level (local) bus is illustrated in
that an external logic on the bus carries out the following functions:
9-42
Each processor has, at most, one reservation flag
lwarx sets the reservation flag
lwarx by the same processor clears the reservation flag related to a previous lwarx instruction and
again sets the reservation flag
stwcx by the same processor clears the reservation flag
Store by the same processor does not clear the reservation flag
Some other processor (or other mechanism) store to the same address as an existing reservation
clears the reservation flag
In case the storage reservation is lost, it is guaranteed that stwcx will not modify the storage
Snoops accesses to all local bus slaves
Holds one reservation for each local master capable of storage reservations
Sets the reservation when that master issues a load and reserve request
Clears the reservation when some other master issues a store to the reservation address
Storage Reservation
MPC561/MPC563 Reference Manual, Rev. 1.2
Figure
9-30. The protocol assumes
Freescale Semiconductor

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