MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 365

• Manufacturer Part Number: MPC562MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC562MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

Freescale Semiconductor
2. Receive Bus Grant (BG) from Arbiter
4. Assert Transfer Start (TS)
6. Drive BURST Asserted
1. Request Bus (BR)
3. Assert Bus Busy (BB) if No Other Master is Driving
5. Drive Address and Attributes
7. MTS Asserted (from MPC500 Device)
Negate Burst Data in Progress (BDIP)
ADDR[28:29] mod 4 =?
Stop Driving Data
External Master
Assert BDIP
= 2
Drive Data
Drive Data
Assert BDIP
Drive Data
= 3
= 1
Drive data
Assert BDIP
= 0
MPC561/MPC563 Reference Manual, Rev. 1.2
Assert Transfer Acknowledge (TA)
Assert Transfer Acknowledge (TA)
Assert Transfer Acknowledge (TA)
Assert Transfer Acknowledge (TA)
Receive Address
BDIP Asserted
BDIP Asserted
BDIP Asserted
BDIP Asserted
Sample Data
Sample Data
Sample Data
Sample Data
Slave
Yes
Yes
Yes
Yes
No
No
No
No
External Bus Interface
Don’t Sample
Next Data
Don’t Sample
Next Data
Don’t Sample
Next Data
Don’t Sample
Next Data
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