MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 358

• Manufacturer Part Number: MPC562MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC562MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

External Bus Interface
The MPC561/MPC563 also supports burst-inhibited transfers for slave devices that are unable to support
bursting. For this type of bus cycle, the selected slave device supplies or samples the first word the
MPC561/MPC563 points to and asserts the burst-inhibit signal with TA for the first transfer of the burst
access. The MPC561/MPC563 responds by terminating the burst and accessing the remainder of the
16-byte block. These remaining accesses use up to three read/write bus cycles (each one for a word) in the
case of a 32-bit port width slave, up to seven read/write bus cycles in the case of a 16-bit port width slave,
or up to fifteen read/write bus cycles in the case of a 8-bit port width slave.
The general case of burst transfers assumes that the external memory has a 32-bit port size. The
MPC561/MPC563 provides an effective mechanism for interfacing with 16-bit and 8-bit port size
memories, allowing bursts transfers to these devices when they are controlled by the internal memory
controller.
In this case, the MPC561/MPC563 attempts to initiate a burst transfer as in the normal case. If the memory
controller signals to the bus interface that the external device has a small port size (8 or 16 bits), and if the
burst is accepted, the bus interface completes a burst of 16 or 8 beats respectively for four words. Eight
words requires 32 or 16 beats. Each beat of the burst transfers only one or two bytes effectively. Note that
this burst of 8 or 16 beats is considered an atomic transaction, so the MPC561/MPC563 does not allow
other unrelated master accesses or bus arbitration to intervene between the transfers.
9.5.5
In addition to the standard bus signals, the MPC561/MPC563 burst mechanism uses the following signals:
At the start of the burst transfer, the master drives the address, the address attributes, and the BURST signal
to indicate that a burst transfer is being initiated, and asserts TS. If the slave is burstable, it negates the
burst-inhibit (BI) signal. If the slave cannot burst, it asserts BI. For additional details, refer to
Section 10.2.5, “Burst
During the data phase of a burst-write cycle, the master drives the data. It also asserts BDIP if it intends to
drive the data beat following the current data beat. When the slave has received the data, it asserts TA to
indicate to the master that it is ready for the next data transfer. The master again drives the next data and
asserts or negates the BDIP signal. If the master does not intend to drive another data beat following the
current one, it negates BDIP to indicate to the slave that the next data beat transfer is the last data of the
burst-write transfer.
BDIP has two basic timings: normal and late (see
assertion of BDIP is delayed by the number of wait states in the first data beat. This implies that for
zero-wait-state cycles, BDIP assertion time is identical in normal and late modes. Cycles with late BDIP
generation can occur only during cycles for which the memory controller generates TA internally. Refer
to
9-18
Chapter 10, “Memory
•
•
•
The BURST signal indicates that the cycle is a burst cycle.
The burst data in progress (BDIP) signal indicates the duration of the burst data.
The burst inhibit (BI) signal indicates whether the slave is burstable.
Burst Mechanism
Support.”
Controller” for more information.
MPC561/MPC563 Reference Manual, Rev. 1.2
Figure 9-14
and
Figure
9-15). In the late timing mode,
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