MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 348

• Manufacturer Part Number: MPC562MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC562MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

External Bus Interface
9.5
This section provides a functional description of the system bus, the signals that control it, and the bus
cycles provided for data transfer operations. It also describes the error conditions, bus arbitration, and reset
operation.
The MPC561/MPC563 generates a system clock output (CLKOUT). This output sets the frequency of
operation for the bus interface directly. Internally, the MPC561/MPC563 uses a phase-lock loop (PLL)
circuit to generate a master clock for all of the MPC561/MPC563 circuitry (including the bus interface)
which is phase-locked to the CLKOUT output signal.
All signals for the MPC561/MPC563 bus interface are specified with respect to the rising edge of the
external CLKOUT and are guaranteed to be sampled as inputs or changed as outputs with respect to that
edge. Since the same clock edge is referenced for driving or sampling the bus signals, the possibility of
clock skew could exist between various modules in a system due to routing or the use of multiple clock
lines. It is the responsibility of the system to handle any such clock skew problems that could occur.
9.5.1
The basic transfer protocol defines the sequence of actions that must occur on the MPC561/MPC563 bus
to perform a complete bus transaction. A simplified scheme of the basic transfer protocol is illustrated in
Figure
The basic transfer protocol provides for an arbitration phase and an address and data transfer phase. The
address phase specifies the address for the transaction and the transfer attributes that describe the
transaction. The data phase performs the transfer of data (if any is to be transferred). The data phase may
transfer a single beat of data (four bytes or less) for nonburst operations, a 4-beat burst of data (4 x 4 bytes),
an 8-beat burst of data (8 x 2 bytes) or a 16-beat burst of data (16 x 1 bytes).
9-8
9-3.
Bus Operations
Signal Name
Basic Transfer Protocol
Arbitration
RETRY
Retry
Table 9-1. MPC561/MPC563 BIU Signals (continued)
Pins
1
MPC561/MPC563 Reference Manual, Rev. 1.2
Address Transfer
Figure 9-3. Basic Transfer Protocol
Active
Low
I/O
O
I
In the case of regular transaction, this signal is driven
by the slave device to indicate that the
MPC561/MPC563 must relinquish the ownership of
the bus and retry the cycle.
When an external master owns the bus and the
internal MPC561/MPC563 bus initiates access to the
external bus at the same time, this signal is used to
cause the external master to relinquish the bus for one
clock to solve the contention.
Data Transfer
Description
Termination
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