MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 337

• Manufacturer Part Number: MPC562MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC562MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

Freescale Semiconductor
22:23
Bits
16
17
18
19
20
21
24
TEXP_INVP Timer Expired Pin Inversed Polarity – The TEX_INVP bit controls whether the polarity of the
SPLSS
TEXPS
TMIST
CSRC
Name
LPM
CSR
—
SPLL lock status sticky bit. An out-of-lock sets the SPLSS bit. The bit remains set until
software clears it by writing a one to it. A write of zero has no effect on this bit. The bit is
cleared at power-on reset. This bit is not affected due to a software initiated loss-of-lock (MF
change and entering deep-sleep or power-down mode). The SPLSS bit is not affected by
hard reset.
0 SPLL has remained in lock
1 SPLL has gone out of lock at least once (not due to software-initiated loss of lock)
Timer expired status bit. This bit controls whether the chip negates the TEXP pin in
deep-sleep mode, thus enabling external circuitry to switch off the VDD (power-down mode).
When LPM = 11, CSRC = 0, and TEXPS is high, the TEXP pin remains asserted. When LPM
= 11, CSRC = 0, and TEXPS is low, the TEXPS pin is negated.
To enable automatic wake-up TEXPS is asserted when one of the following occurs:
0 TEXP is negated in deep-sleep mode
1 TEXP pin remains asserted always
TEXP pin will be active high (normal default) or active low.
0 The TEXP pin is active high
1 The TEXP pin is active low
Timers interrupt status.TMIST is set when an interrupt from the RTC, PIT, TB or DEC occurs.
The TMIST bit is cleared by writing a one to it. Writing a zero has no effect on this bit. The
system clock frequency remains at its high frequency value (defined by DFNH) if the TMIST
bit is set, even if the CSRC bit in the PLPRCR is set (DFNL enabled) and conditions to switch
to normal-low mode do not exist. This bit is cleared during power-on or hard reset.
0 No timer expired event was detected
1 A timer expire event was detected
Reserved
Clock source. This bit is cleared at hard reset.
0 General system clock is determined by the DFNH value
1 General system clock is determined by the DFNL value
Low-power mode select. These bits are encoded to provide one normal operating mode and
four low-power modes. In normal and doze modes, the system can be in high state
(frequency determined by the DFNH bits) or low state (frequency defined by the DFNL bits).
The LPM field can be write-protected by setting the LPM and CSRC lock (LPML) bit in the
SCCR Refer to
Checkstop reset enable. If this bit is set, then an automatic reset is generated when the
RCPU signals that it has entered checkstop mode, unless debug mode was enabled at reset.
If the bit is clear and debug mode is not enabled, then the USIU will not do anything upon
receiving the checkstop signal from the RCPU. If debug mode is enabled, then the part
enters debug mode upon entering checkstop mode. In this case, the RCPU will not assert
the checkstop signal to the reset circuitry. This bit is writable once after soft reset.
0 No reset will occur when checkstop is asserted
1 Reset will occur when checkstop is asserted
• The PIT is expired
• The real-time clock alarm is set
• The time base clock alarm is set
• The decrementer exception occurs
• The bit remains set until software clears it by writing a one to it. A write of zero has no
effect on this bit. TEXPS is set by power-on or hard reset.
Table 8-11. PLPRCR Bit Descriptions (continued)
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 8-4
and
Table
8-5.
Description
Clocks and Power Control
8-35