MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 306

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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Clocks and Power Control
8.2.1
The PLL can multiply the input frequency by any integer between one and 4096. The multiplication factor
depends on the value of the MF[0:11] bits in the PLPRCR register. While any integer value from one to
4096 can be programmed, the resulting VCO output frequency must be at least 15 MHz. The multiplication
factor is set to a predetermined value during power-on reset as defined in
8.2.2
The PLL is capable of eliminating the skew between the external clock entering the chip (EXTCLK) and
both the internal clock phases and the CLKOUT pin, making it useful for tight synchronous timings. Skew
elimination is active only when the PLL is enabled and programmed with a multiplication factor of one or
two (MF = 0 or 1). The timing reference to the system PLL is the external clock input (EXTCLK pin).
8.2.3
A pre-divider before the phase comparator enables additional system clock resolution when the crystal
oscillator frequency is 20 MHz. The division factor is determined by the DIVF[0:4] bits in the PLPRCR.
8.2.4
As shown in
comparator controls the direction (up or down) that the charge pump drives the voltage across the external
filter capacitor (XFC). The direction depends on whether the feedback signal phase lags or leads the
reference signal. The output of the charge pump drives the VCO. The output frequency of the VCO is
divided down and fed back to the phase comparator for comparison with the reference signal, OSCCLK.
The MF values, zero to 4095, are mapped to multiplication factors of one to 4096. Note that when the PLL
is operating in 1:1 mode (refer to
frequency is twice the maximum system frequency. This double frequency is needed to generate GCLK1
and GCLK2 clocks. On power-up, with a 4-MHz or 20-MHz crystal and the default MF settings,
VCOOUT will be 40 MHz and the system clock will be 20 MHz.
The equation for VCOOUT is:
In the case of initial system power up, or if KAPWR is lost, an external circuit must assert power on reset
(PORESET). Once KAPWR is valid, PORESET must be asserted long enough to allow the external
oscillator to start up and stabilize for the device to come out of reset in normal (non limp) mode.
8-4
Frequency Multiplication
Skew Elimination
Pre-Divider
PLL Block Diagram
Figure
When operating with the backup clock, the system clock (and CLKOUT) is
one-half of the ring oscillator frequency, (i.e., the system clock is
approximately 11 MHz). The time base and PIT clocks will be twice the
system clock frequency.
8-3, the reference signal, OSCCLK, goes to the phase comparator. The phase
VCOOUT =
MPC561/MPC563 Reference Manual, Rev. 1.2
Table
8-1), the multiplication factor is one (MF = 0). The PLL output
OSCCLK
DIVF + 1
NOTE
x (MF + 1) x 2
Table
8-1.
Freescale Semiconductor

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