MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 305

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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8.1
The system clock can be provided by the main system oscillator, an external clock input, or the backup
clock (BUCLK) on-chip ring oscillator, see
The main system oscillator uses either a 4-MHz or 20-MHz crystal to generate the PLL reference clock.
When the main system oscillator output is the timing reference to the system PLL, skew elimination
between the XTAL/EXTAL pins and CLKOUT is not guaranteed. There is also an on-chip crystal
feedback resistor on the MPC561/MPC563; however, space should be reserved for an off-chip resistor to
allow for future configurations.
The external clock input (EXTCLK pin) can receive a clock signal from an external source. The clock
frequency must be in the range of 3-5 MHz or, for 1:1 mode, at the system frequency of at least 15 MHz.
When the external clock input is the timing reference to the system PLL, the skew between the EXTCLK
pin and the CLKOUT is less than
The backup clock on-chip ring oscillator allows the MPC561/MPC563 to function with a less precise
clock. When operating from the backup clock, the MPC561/MPC563 is in limp mode. This enables the
system to continue minimum functionality until the system is fixed. The BUCLK frequency is
approximately 11 MHz for the MPC561/MPC563 (see
complete frequency range).
For normal operation, at least one clock source (EXTCLK or main system oscillator) must be active. A
configuration with both clock sources active is possible as well. At this configuration EXTCLK provides
the system clock and main system oscillator provides the PITRTCLK. The input of an unused timing
reference (EXTCLK or EXTAL) must be grounded.
8.2
The PLL allows the processor to operate at a high internal clock frequency using a low frequency clock
input, a feature which offers two benefits: reduces the overall electromagnetic interference generated by
the system, and the ability to oscillate at different frequencies reduces cost by eliminating the need to add
an additional oscillator to a system.
The PLL can perform the following functions:
Freescale Semiconductor
1. Resistor is not currently required on the board but space should be available for its addition in the future.
Frequency multiplication
Skew elimination
Frequency division
System Clock Sources
System PLL
Figure 8-2. Main System Oscillator Crystal Configuration
Figure 8-2
MPC561/MPC563 Reference Manual, Rev. 1.2
±
1 ns.
CL
XTAL
illustrates the main system oscillator crystal configuration.
Figure
1 M
8-1.
1
EXTAL
Appendix F, “Electrical
CL
Characteristics” for the
Clocks and Power Control
8-3

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