MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 258

• Manufacturer Part Number: MPC562MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC562MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

System Configuration and Protection
MPC561/MPC563, and RCPU access is terminated with a data error, causing a machine check state or
exception.
The bus monitor timing bit in the system protection control register (SYPCR[BMT]) defines the bus
monitor time-out period. The programmability of the time-out allows for variation in system peripheral
response time. The timing mechanism is clocked by the external bus clock divided by eight. The maximum
value is 2040 system clock cycles.
SYPCR[BME] enables or disables the bus monitor. But regardless of the state of this bit the bus monitor
is always enabled when freeze is asserted in debug mode.
6.1.6
The decrementer (DEC) is a 32-bit decrementing counter defined by the MPC561/MPC563 architecture
to provide a decrementer interrupt. This binary counter is clocked by the same frequency as the time base
(also defined by the MPC500 architecture). The operation of the time base and decrementer are therefore
coherent. The DEC is clocked by the TMBCLK clock. The decrementer period is computed as follows:
The state of the DEC is not affected by any resets and should be initialized by software. The DEC runs
continuously after power-up once the time base is enabled by setting the TBE bit of the TBSCR (see
Table
counting while reset is asserted.
Reading from the decrementer has no effect on the counter value. Writing to the decrementer replaces the
value in the decrementer with the value in the GPR.
Whenever bit 0 (the MSB) of the decrementer changes from zero to one, a decrementer exception occurs.
If software alters the decrementer such that the content of bit 0 is changed to a value of 1, a decrementer
exception occurs.
A decrementer exception causes a decrementer interrupt request to be pending in the RCPU. When the
decrementer exception is taken, the decrementer interrupt request is automatically cleared.
Table 6-6
crystal, and TBS = 0 which selects TMBCLK division to 4.
6-18
6-18) (unless the clock module is programmed to turn off the clock). The decrementer continues
illustrates some of the periods available for the decrementer, assuming a 4-MHz or 20-MHz
Decrementer (DEC)
Time base must be enabled to use the decrementer. See
“Time Base Control and Status Register
0
9
Count Value
Table 6-6. Decrementer Time-Out Periods
MPC561/MPC563 Reference Manual, Rev. 1.2
T
DEC
Time-Out @ 4 MHz
=
NOTE
1.0 µs
10 µs
F
TMBCLK
2
(TBSCR),” for more information.
32
Time-Out @ 20 MHz
Section 6.2.2.4.4,
0.2 µs
2.0 µs
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