MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 210

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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Burst Buffer Controller 2 Module
4.1.4
4.1.5
4.2
4.2.1
The BBC provides two instruction fetch modes: decompression off and decompression on. The operational
modes are defined by RCPU MSR[DCMPEN] bit. If the bit is set, the mode is decompression on.
Otherwise, it is in decompression off.
4.2.1.1
In this mode, the BBC bus interface unit (BIU) module transfers fetch accesses from the RCPU to the
U-bus. When a new access is issued by the RCPU, it is transferred in parallel to both the IMPU and the
BIU. The IMPU compares the address of the access to its region programming. The BIU checks if the
access can be immediately transferred to the U-bus, otherwise it requests the U-bus for the next clock.
4-4
— No performance penalty during sequential program flow execution
— Minimal performance penalty due to change of program flow execution
Two operation modes are available: decompression on and decompression off. Switch between
compressed and non-compressed user application software parts is possible.
Adaptive vocabularies scheme is supported; each user application can have its own optimum
vocabularies.
2 Kbytes RAM for decompression vocabulary tables
2 clock read/write accesses when used as a U-bus general-purpose RAM
4 clock load/store accesses from the L-bus
Byte, half-word (16-bit) or word (32-bit) read/write accesses and fetches
Special access protection functions
Low-power standby operation for data retention
Consists of eight “branch target entries” (BTE). Each entry contains:
— A 32-bit register that stores the target of historical change of flow (COF) address
— Four RAM entries, 38 bits each, which hold up to four valid instruction OPCODES (32 bits).
— A 32-bit register that stores the values used to calculate the address following the last valid
FIFO removal policy management is implemented for the eight BTEs
Software-controlled BTB enable/disable and invalidate
User transparent (that is, no user management is required)
Operation Modes
The six extra bits are used by ICDU in decompression on mode.
instruction.
DECRAM Key Features
Branch Target Buffer Key Features
Instruction Fetch
Decompression Off Mode
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor

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