MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 182

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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Central Processing Unit
The instruction pipeline in the MPC561/MPC563 has four stages:
The history buffer maintains the correct architectural machine state. An exception is taken only when the
instruction is ready to be retired from the machine (i.e., after all previously-issued instructions have
already been retired from the machine). When an exception is taken, all instructions following the
excepting instruction are canceled, (i.e., the values of the affected destination registers are restored using
the values saved in the history buffer during the dispatch stage).
Figure 3-19
Table 3-20
from the time an instruction begins execution until it produces a result that is available for use by a
3-38
1. The dispatch stage is implemented using a distributed mechanism. The central dispatch unit
2. In the execute stage, each execution unit that has an executable instruction executes the instruction.
3. In the writeback stage, the execution unit writes the result to the destination register and reports to
4. In the retirement stage, the history buffer retires instructions in architectural order. An instruction
FETCH
DECODE
READ AND EXECUTE
WRITE BACK (TO DEST REG)
L ADDRESS DRIVE
L DATA
LOAD WRITE BACK
BRANCH DECODE
BRANCH EXECUTE
broadcasts the instruction to all units. In addition, scoreboard information (regarding data
dependencies) is broadcast to each execution unit. Each execution unit decodes the instruction. If
the instruction is not implemented, a program exception is taken. If the instruction is legal and no
data dependency is found, the instruction is accepted by the appropriate execution unit, and the data
found in the destination register is copied to the history buffer. If a data dependency exists, the
machine is stalled until the dependency is resolved.
(For some instructions, this occurs over multiple cycles.)
the history buffer that the instruction is completed.
retires from the machine if it completes execution with no exceptions and if all instructions
preceding it in the instruction stream have finished execution with no exceptions. As many as six
instructions can be retired in one clock.
indicates the latency and blockage for each type of instruction. Latency refers to the interval
shows basic instruction pipeline timing.
MPC561/MPC563 Reference Manual, Rev. 1.2
i1
Figure 3-19. Basic Instruction Pipeline
i1
i1
i1
i2
i1
i1
i2
i1
store
i3
i2
load
i1
i2
Freescale Semiconductor

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