MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 1405

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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DTA1 24-17
DTA2 24-17
DTL 15-19
DTPU 19-20
E
EA 3-34
EBRK 23-43
ECR 23-41
EE bit 3-21
EEPROM mapping 10-24
Effective address 3-34
EIBADR 4-25
EID 3-25
EIE 3-25
ELE bit 3-21
EMCR 6-29
EMPTY
EMU 19-4
Emulation
Encoded
Ending queue pointer (ENDQP) 15-20
End-of-
End-of-queue condition 13-29
ENDQP 15-20
ENGCLK 8-14
Entry
EOF 16-17
EOQ 13-40
EP bit 3-21
ERRINT 16-35
Error
Error counters 16-10
ESTAT 16-33
ETBANK 19-20
ETRIG 13-67
Event timing 19-3
Exception cause register 23-41
Exception prefix 3-21
exception table 4-7
Exceptions 3-34
Freescale Semiconductor
receive message buffer code 16-5
control (EMU) 19-11
support 19-4
one of three channel priority levels (CH) 19-18
time function for each channel (CHANNEL) 19-16
type of host service (CH) 19-18
frame (EOF) 16-17
table bank select field (ETBANK) 19-20
conditions 15-57
interrupt (ERRINT) 16-35
resulting from leakage 13-75
,
,
,
,
19-11
3-22
3-25
14-41
,
,
13-71
15-25
,
14-66
,
3-22
,
14-69
,
,
14-30
14-73
MPC561/MPC563 Reference Manual, Rev. 1.2
exceptions
Execution units 3-4
Extended message format 16-1
External
external
external device
External interrupt 3-48
external interrupt
external master
external master control register (EMCR) 6-29
Externally
EXTI 23-42
EXTIE 23-44
F
Fast quadrature decode TPU function (FQD) D-35
Fault confinement state (FCS) 16-11
FCS 16-11
FE 15-50
FE bits 3-21
features
alignment 3-49
classes 3-35
decrementer 3-53
external interrupt 3-48
little endian mode 3-21
ordered 3-35
precise 3-36
program 3-51
system call 3-54
unordered 3-35
vector table 3-36
compressed address generation A-6
data storage 3-48
frames 16-4
interrupt
leakage 13-76
trigger continuous-scan mode 13-46
trigger pins 13-67
trigger single-scan mode 13-43
interface
arbitration phase 9-32
priority of 9-35
USIU address decoding 6-6
enable 3-21
enhanced 4-10
memory controller 10-28
multiplexed mode (MUX) 13-15
BIU 4-2
disable 3-25
enable 3-25
UC3F 21-4
,
15-57
,
16-34
,
3-22
,
3-25
,
14-73
,
14-66
,
14-44
,
16-34
,
14-47
Index-5

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