MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 1366

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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66-MHz Electrical Characteristics
Note: After reset MCPSMSCR_PSL[3:0] is set to 0b0000.
Note: VS_PCLK is the MIOS prescaler clock which is distributed to all the counter (e.g., MPWMSM and
G.21.1
Note: All delays are in system clock periods.
G-60
1
MCPSM enable to VS_PCLK pulse
PWMSM output resolution
PWM output pulse
MPWMI input pin to MPWMSCR_PIN
status set
CPSM enable to output set
MPWMSM Enable to output set (MIN)
Note 1: f
Note 2: The numbers associated with the f
Note 3: vs_pclk is the MIOS prescaler clock which is distributed around the MIOS to counter modules such as the
MMCSM) submodules.
The MCPSM clock prescaler value (MCPSMSCR_PSL[3:0]) should be written to the MCPSMSCR (MCPSM
Status/Control Register) before rewriting the MCPSMSCR to set the enable bit (MCPSMSCR_PREN). If this is not
done the prescaler will start with the old value in the MCPSMSCR_PSL[3:0] before reloading the new value into the
counter.
Prescaler enable
MIOB VS_PCLK
MMCSM and MPWMSM.
MPWMSM Timing Characteristics
SYS
bit (PREN)
Characteristic
Characteristic
is the internal system clock for the IMB3 bus.
f
SYS
3
Figure G-46. MCPSM Enable to VS_PCLK Pulse Timing Diagram
4
Table G-24. MPWMSM Timing Characteristics
Table G-23. MCPSM Timing Characteristics
MPC561/MPC563 Reference Manual, Rev. 1.2
1
5
SYS
Symbol
Symbol
t
t
t
CPSMC
t
t
t
PWMO
CPSMC
PWMR
PWMP
PWME
ticks refer to the IMB3 internal state.
t
PIN
(MPWMPERR - MPWMPULR + 1) *
(256 - MPWMSCR_CP) * MCPSMSCR_PSL + 1
(MPWMPERR - MPWMPULR) * (256 - MPWMSCR_CP) *
MCPSMSCR_PSL + 3 +
(255 - MPWMSCR_CP) * MCPSMSCR_PSL
(MCPSMSCR_PSL[3:0]) -1
Min
2.0
1
1
Delay
Freescale Semiconductor
2.0
Max
2
6
System Clock
2
Cycles
Unit

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