MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 1209

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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D.20.1.6
This parameter is the data register for all SIOP transfers. Data is shifted out of one end of SIOP_DATA
and shifted in at the other end, the shift direction being determined by the value of BIT_D. In output-only
mode, zero will be shifted into SIOP_DATA and in input-only mode, the data shifted out is ignored. In
clock-only mode, SIOP_DATA is still shifted.
D.20.2
The RCPU initializes the SIOP function by:
The TPU3 then starts the data transfer, and issues an interrupt request when the transfer is complete.
Once the function has been initialized, the RCPU only needs to write SIOP_DATA with the new data and
issue a HSR 0b11 to initiate a new transfer. In input-only or clock-only modes, just the HSR 0b11 is
required.
D.20.3
Like all TPU3 functions, the performance limit of the SIOP function depends, because of the operational
nature of the scheduler, on the service time (latency) associated with other active TPU3 channels. Where
two channels are used for a uni-directional system and no other TPU3 channels are active, the maximum
baud rate is approximately 230 at a bus speed of 16.77 MHz. A three-channel bidirectional system under
the same conditions has a maximum baud rate of approximately 200. When more TPU3 channels are
Freescale Semiconductor
1. Disabling the channel by clearing the two channel-priority bits
2. Selecting the SIOP function on the channel by writing the assigned SIOP function number to the
3. Writing CHAN_CONTROL in the clock channel parameter RAM
4. Writing HALF_PERIOD, BIT_D, and XFER_SIZE in the clock-channel parameter RAM to
5. Writing SIOP_DATA if the data output is to be used
6. Selecting the required operating mode via the two host-sequence bits
7. Issuing a host service request type 0b11
8. Enabling service by assigning H, M, or L priority to the clock channel via the two channel-priority
function-select bits
determine the speed, shift direction, and size of the transfer
bits
Host RCPU Initialization of the SIOP Function
SIOP Function Performance
SIOP_DATA
The TPU3 does not “justify” the data position in SIOP_DATA (for example,
if an 8-bit bidirectional transfer is made, shifting LSB first, then the bottom
byte of SIOP_DATA will be shifted out and the input data will be shifted
into the upper byte of SIOP_DATA).
SIOP_DATA is not buffered. The RCPU should only access it between
completion of one transfer and the start of the next.
MPC561/MPC563 Reference Manual, Rev. 1.2
NOTE
NOTE
TPU3 ROM Functions
D-57

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