MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 1154

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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TPU3 ROM Functions
these entry tables the RCPU selects. Though the TPU3 can access either entry table, only one table can be
used at a time and functions from the tables cannot be mixed. The default entry table, located in bank 0, is
identical to the standard microcode ROM in the TPU2, making any RCPU code written for the TPU2
interchangable with the TPU3. The functions in the default entry table in bank 0 are listed in
The functions in the bank 1 entry table are identical to those in bank 0, except in three cases. Function 1,
SPWM in the bank 0 table, has been replaced by RWTPIN, a function that allows a read and write to the
TPU3 timebases and corresponding pin. Function 5, PPWA in the bank 0 table, is an identification (ID)
function in the bank 1 table that provides the microcode ROM revision number. Function 7, MCPWM, has
been replaced by MULTI in later silicon revisions. The functions in the bank 1 entry table are listed in
Table
The RCPU selects which entry table to use by setting the ETBANK field in the TPUMCR2 register. This
register is written once after reset. Although one entry table is specified at start-up, in some cases it is
possible to use functions from both tables without resetting the microcontroller. A customer may, for
example, wish to use the ID function from bank 1 to verify the TPU3 microcode version but then use the
MCPWM function from bank 0. As a customer will typically only run the ID function during system
D-2
1
The MULTI functions are only on revision D and later of the MPC561 and not available on revision B and earlier of
the MPC563.
D-1.
Function
Number
0xD
0xC
0xF
0xE
0xB
0xA
9
8
7
6
5
4
3
2
1
0
MCPWM (Multi-Channel Pulse Width Modulation)
SPWM (Synchronized Pulse Width Modulation)
NITC (New Input Capture/Input Transition
PPWA (Period/Pulse Width Accumulator)
COMM (Multiphase Motor Commutation)
PTA (Programmable Time Accumulator)
FQM (Frequency Measurement)
UART (Universal Asynchronous
FQD (Fast Quadrature Decode)
PWM (Pulse Width Modulation)
SIOP (Serial Input/Output Port)
QOM (Queued Output Match)
Bank 0 Functions (Default)
HALLD (Hall Effect Decode)
DIO (Discrete Input/Output)
TSM (Table Stepper Motor)
OC (Output Compare)
Receiver/Transmitter)
Table D-1. Bank 0 and Bank 1 Functions
MPC561/MPC563 Reference Manual, Rev. 1.2
Counter)
NITC (New Input Capture/Input Transition
COMM (Multiphase Motor Commutation)
PTA (Programmable Time Accumulator)
RWTPIN (Read/Write Timers and Pin)
FQM (Frequency Measurement)
UART (Universal Asynchronous
FQD (Fast Quadrature Decode)
PWM (Pulse Width Modulation)
SIOP (Serial Input/Output Port)
QOM (Queued Output Match)
HALLD (Hall Effect Decode)
DIO (Discrete Input/Output)
TSM (Table Stepper Motor)
OC (Output Compare)
Receiver/Transmitter)
MULTI (Multi TPU)
Bank 1 Functions
ID (Identification)
Counter)
Freescale Semiconductor
1
Table
D-1.

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