MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 1056

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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IEEE 1149.1-Compliant Interface (JTAG)
The TAP consists of five dedicated signal pins, a 16-state TAP controller, and two test data registers. A
boundary scan register links all device signal pins into a single shift register. The test logic implemented
utilizes static logic design. The MPC561/MPC563 implementation provides the capability to:
25.1.1
An overview of the MPC561/MPC563 scan chain implementation is shown in
MPC561/MPC563 implementation includes a TAP controller, a 4-bit instruction register, and two test
registers (a one-bit bypass register and a 427-bit (MPC563) or 423-bit (MPC561) boundary scan register).
This implementation includes a dedicated TAP consisting of the following signals:
25-2
1. Perform boundary scan operations to test circuit-board electrical continuity.
2. Bypass the MPC561/MPC563 for a given circuit-board test by effectively reducing the boundary
3. Sample the MPC561/MPC563 system pins during operation and transparently shift out the result
4. Disable the output drive to pins during circuit-board testing.
scan register to a single cell.
in the boundary scan register.
TCK — a test clock input to synchronize the test logic. (with an internal pull-down resistor)
TMS — a test mode select input (with an internal pullup resistor) that is sampled on the rising edge
of TCK to sequence the TAP controller’s state machine.
TDI — a test data input (with an internal pullup resistor) that is sampled on the rising edge of TCK.
TDO — a three-state test data output that is actively driven in the shift-IR and shift-DR controller
states. TDO changes on the falling edge of TCK. (This pin also has a weak pull-up that is active
when output drivers are disabled, except during a HI-Z instruction).
TRST — an asynchronous reset with an internal pull-up resistor that provides initialization of the
TAP controller and other logic required by the standard. This input is multiplexed with the
PORESET signal.
JCOMP — JTAG Compliancy – This signal provides JTAG IEEE1149.1 compatibility and selects
between normal operation (low) and JTAG test mode (high).
Overview
Certain precautions must be observed to ensure that the IEEE 1149-like test
logic does not interfere with nontest operation. JCOMP must be low prior to
PORESET assertion after low power mode exits, otherwise an unknown
state will occur.
JTAG mode does not provide access to the internal MPC561/MPC563
circuitry. It allows access only to the input or output pad (periphery)
circuitry.
MPC561/MPC563 Reference Manual, Rev. 1.2
NOTE
NOTE
Figure
Freescale Semiconductor
25-2. The

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