MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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MPC561/MPC563 Reference Manual
Additional Devices Supported:
MPC562
MPC564
MPC561RM
REV 1.2
08/2005

MPC562MZP56 Summary of contents

Page 1

MPC561/MPC563 Reference Manual Additional Devices Supported: MPC562 MPC564 MPC561RM REV 1.2 08/2005 ...

Page 2

... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended ...

Page 3

... MPC561/MPC563 Optional Features ............................................................................. 1-9 1.5 Comparison of MPC561/MPC563 and MPC555 ........................................................... 1-9 1.6 Additional MPC561/MPC563 Differences ................................................................... 1-10 1.7 SRAM Keep-Alive Power Behavior ............................................................................. 1-11 1.8 MPC561/MPC563 Address Map .................................................................................. 1-11 Freescale Semiconductor Contents Title About This Book lxxvii Chapter 1 Overview MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number ...

Page 4

... Integer Unit (IU) ......................................................................................................... 3-5 3.4.3 Load/Store Unit (LSU) ............................................................................................... 3-6 3.4.4 Floating-Point Unit (FPU) .......................................................................................... 3-6 3.5 Levels of the PowerPC ISA Architecture ....................................................................... 3-6 3.6 RCPU Programming Model ............................................................................................ 3-7 Freescale Semiconductor Contents Title Chapter 2 Signal Descriptions Chapter 3 Central Processing Unit MPC561/MPC563 Reference Manual, Rev. 1.2 Page ...

Page 5

... Unordered Exceptions ............................................................................................... 3-35 3.11.4 Precise Exceptions .................................................................................................... 3-36 3.11.5 Exception Vector Table ............................................................................................ 3-36 3.12 Instruction Timing ........................................................................................................ 3-37 3.13 User Instruction Set Architecture (UISA) .................................................................... 3-39 3.13.1 Computation Modes .................................................................................................. 3-39 3.13.2 Reserved Fields ......................................................................................................... 3-39 Freescale Semiconductor Contents Title MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number v ...

Page 6

... System Reset Exception and NMI (0x0100) ........................................................ 3-45 3.15.4.2 Machine Check Exception (0x0200) .................................................................... 3-46 3.15.4.3 Data Storage Exception (0x0300) ......................................................................... 3-48 3.15.4.4 Instruction Storage Exception (0x0400) ............................................................... 3-48 3.15.4.5 External Interrupt (0x0500) .................................................................................. 3-48 Freescale Semiconductor Contents Title MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number vi ...

Page 7

... Decompressor RAM (DECRAM) Functionality .......................................................... 4-12 4.4.1 General-Purpose Memory Operation ........................................................................ 4-13 4.4.1.1 Memory Protection Violations ............................................................................. 4-14 4.4.1.2 DECRAM Standby Operation Mode .................................................................... 4-14 4.5 Branch Target Buffer .................................................................................................... 4-14 Freescale Semiconductor Contents Title Chapter 4 Burst Buffer Controller 2 Module MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number vii ...

Page 8

... Interrupt Configuration ........................................................................................... 6-8 6.1.4.3 Regular Interrupt Controller Operation (MPC555/MPC556-Compatible Mode) 6-10 6.1.4.4 Enhanced Interrupt Controller Operation ............................................................. 6-11 6.1.4.4.1 Lower Priority Request Masking ...................................................................... 6-14 6.1.4.4.2 Backward Compatibility with MPC555/MPC556 ............................................ 6-14 Freescale Semiconductor Contents Title Chapter 5 Chapter 6 MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number viii ...

Page 9

... Real-Time Clock Alarm Register (RTCAL) .................................................... 6-44 6.2.2.4.8 Periodic Interrupt Status and Control Register (PISCR) .................................. 6-44 6.2.2.4.9 Periodic Interrupt Timer Count Register (PITC) .............................................. 6-45 6.2.2.4.10 Periodic Interrupt Timer Register (PITR) ........................................................ 6-45 Freescale Semiconductor Contents Title MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number ix ...

Page 10

... Pre-Divider .................................................................................................................. 8-4 8.2.4 PLL Block Diagram .................................................................................................... 8-4 8.2.5 PLL Pins ..................................................................................................................... 8-5 8.3 System Clock During PLL Loss of Lock ........................................................................ 8-6 8.4 Low-Power Divider ........................................................................................................ 8-6 Freescale Semiconductor Contents Title Chapter 7 Reset Chapter 8 Clocks and Power Control MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number ...

Page 11

... Clocks Unit Programming Model ................................................................................. 8-29 8.11.1 System Clock Control Register (SCCR) ................................................................... 8-29 8.11.2 PLL, Low-Power, and Reset-Control Register (PLPRCR) ...................................... 8-33 8.11.3 Change of Lock Interrupt Register (COLIR) ............................................................ 8-36 8.11.4 IRAMSTBY Control Register (VSRMCR) .............................................................. 8-37 Freescale Semiconductor Contents Title MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number xi ...

Page 12

... Termination Signals Protocol ............................................................................... 9-40 9.5.10 Storage Reservation .................................................................................................. 9-42 9.5.11 Bus Exception Control Cycles .................................................................................. 9-45 9.5.11.1 Retrying a Bus Cycle ............................................................................................ 9-45 9.5.11.2 Termination Signals Protocol Summary ............................................................... 9-49 Freescale Semiconductor Contents Title Chapter 9 External Bus Interface MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number xii ...

Page 13

... Memory Controller Base Registers (BR0–BR3) .................................................... 10-32 10.9.4 Memory Controller Option Registers (OR0–OR3) ................................................ 10-34 10.9.5 Dual-Mapping Base Register (DMBR) .................................................................. 10-36 10.9.6 Dual-Mapping Option Register (DMOR) ............................................................... 10-37 Freescale Semiconductor Contents Title Chapter 10 Memory Controller MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number ...

Page 14

... Global Region Attribute Register (L2U_GRA) ...................................................... 11-16 U-Bus to IMB3 Bus Interface (UIMB) 12.1 Features ......................................................................................................................... 12-1 12.2 UIMB Block Diagram .................................................................................................. 12-2 12.3 Clock Module ............................................................................................................... 12-2 12.4 Interrupt Operation ....................................................................................................... 12-3 Freescale Semiconductor Contents Title Chapter 11 L-Bus to U-Bus Interface (L2U) Chapter 12 MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number xiv ...

Page 15

... Conversion Cycle Times ..................................................................................... 13-35 13.4.1.2 Amplifier Bypass Mode Conversion Timing ..................................................... 13-35 13.4.2 Channel Decode and Multiplexer ........................................................................... 13-36 13.4.3 Sample Buffer Amplifier ........................................................................................ 13-36 13.4.4 Digital-to-Analog Converter (DAC) Array ............................................................ 13-36 Freescale Semiconductor Contents Title Chapter 13 MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number xv ...

Page 16

... Analog Input Signals .............................................................................................. 13-71 13.7.5.1 Analog Input Considerations .............................................................................. 13-73 13.7.5.2 Settling Time for the External Circuit ................................................................ 13-75 13.7.5.3 Error Resulting from Leakage ............................................................................ 13-75 13.7.5.4 Accommodating Positive/Negative Stress Conditions ....................................... 13-76 Freescale Semiconductor Contents Title MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number xvi ...

Page 17

... State Machine ......................................................................................................... 14-38 14.4 Digital Subsystem ....................................................................................................... 14-38 14.4.1 Queue Priority ......................................................................................................... 14-39 14.4.2 Sub-Queues That are Paused .................................................................................. 14-39 14.4.3 Boundary Conditions .............................................................................................. 14-41 14.4.4 Scan Modes ............................................................................................................. 14-42 14.4.4.1 Disabled Mode .................................................................................................... 14-42 Freescale Semiconductor Contents Title Chapter 14 MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number xvii ...

Page 18

... Block Diagram .............................................................................................................. 15-1 15.2 Key Features ................................................................................................................. 15-2 15.2.1 MPC561/MPC563 QSMCM Details ........................................................................ 15-3 15.3 Memory Maps ............................................................................................................... 15-4 15.4 QSMCM Global Registers ............................................................................................ 15-6 15.4.1 Low-Power Stop Operation ...................................................................................... 15-6 15.4.2 Freeze Operation ....................................................................................................... 15-6 Freescale Semiconductor Contents Title Chapter 15 MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number xviii ...

Page 19

... Master Wraparound Mode .................................................................................. 15-38 15.6.6 Slave Mode ............................................................................................................. 15-39 15.6.6.1 Description of Slave Operation .......................................................................... 15-40 15.6.7 Slave Wraparound Mode ........................................................................................ 15-41 15.6.8 Mode Fault .............................................................................................................. 15-42 15.7 Serial Communication Interface ................................................................................. 15-42 15.7.1 SCI Registers .......................................................................................................... 15-45 Freescale Semiconductor Contents Title MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number xix ...

Page 20

... Example QSCI1 Receive Operation of 17 Data Frames ......................................... 15-75 16.1 Features ......................................................................................................................... 16-1 16.2 External Signals ............................................................................................................ 16-2 16.2.1 TouCAN Signal Sharing ........................................................................................... 16-3 16.3 TouCAN Architecture ................................................................................................... 16-3 16.3.1 Tx/Rx Message Buffer Structure .............................................................................. 16-4 Freescale Semiconductor Contents Title Chapter 16 CAN 2.0B Controller Module MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number xx ...

Page 21

... Receive Buffer 14 Mask Registers (RX14MSKHI, RX14MSKLO) ...................... 16-32 16.7.11 Receive Buffer 15 Mask Registers (RX15MSKHI, RX15MSKLO) ...................... 16-33 16.7.12 Error and Status Register (ESTAT) ........................................................................ 16-33 16.7.13 Interrupt Mask Register (IMASK) .......................................................................... 16-35 Freescale Semiconductor Contents Title MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number xxi ...

Page 22

... MMCSM Features .................................................................................................. 17-20 17.8.1.1 MMCSM Signal Functions ................................................................................. 17-21 17.8.2 MMCSM Prescaler ................................................................................................. 17-21 17.8.3 Modular I/O Bus (MIOB) Interface ........................................................................ 17-21 17.8.4 Effect of RESET on MMCSM ................................................................................ 17-22 17.8.5 MMCSM Registers ................................................................................................. 17-22 Freescale Semiconductor Contents Title Chapter 17 MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number xxii ...

Page 23

... Pulse Width Registers ......................................................................................... 17-50 17.10.3.5 Duty Cycles (0% and 100%) .............................................................................. 17-51 17.10.3.6 Pulse/Frequency Range Table ............................................................................ 17-52 17.10.3.7 MPWMSM Status and Control Register (SCR) ................................................. 17-53 17.10.3.8 MPWMSM Interrupt .......................................................................................... 17-53 17.10.3.9 MPWMSM Port Functions ................................................................................. 17-54 Freescale Semiconductor Contents Title MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number xxiii ...

Page 24

... MIOS14 Function Examples ...................................................................................... 17-70 17.13.1 MIOS14 Input Double Edge Pulse Width Measurement ........................................ 17-70 17.13.2 MIOS14 Input Double Edge Period Measurement ................................................. 17-71 17.13.3 MIOS14 Double Edge Single Output Pulse Generation ......................................... 17-72 Freescale Semiconductor Contents Title MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number xxiv ...

Page 25

... Short Channels Register (SHORT_CH_REG) ...................................................... 18-22 18.4.12 Scale Transmit Clock Register (SCALE_TCLK_REG) ........................................ 18-24 19.1 Overview ....................................................................................................................... 19-2 19.2 TPU3 Components ........................................................................................................ 19-2 19.2.1 Time Bases ................................................................................................................ 19-2 Freescale Semiconductor Contents Title Chapter 18 Chapter 19 Time Processor Unit 3 MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number xxv ...

Page 26

... Features ......................................................................................................................... 20-1 20.2 DPTRAM Configuration Block Diagram ..................................................................... 20-2 20.3 Programming Model ..................................................................................................... 20-2 20.3.1 DPTRAM Module Configuration Register (DPTMCR) ......................................... 20-3 20.3.2 DPTRAM Test Register (DPTTCR) ......................................................................... 20-4 Freescale Semiconductor Contents Title Chapter 20 Dual-Port TPU3 RAM (DPTRAM) MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number xxvi ...

Page 27

... High Voltage Operations ........................................................................................ 21-21 21.3.6.1 Overview of Program/Erase Operation .............................................................. 21-21 21.3.7 Programming .......................................................................................................... 21-21 21.3.7.1 Program Sequence .............................................................................................. 21-22 21.3.7.2 Program Shadow Information ............................................................................. 21-24 21.3.7.3 Program Suspend ................................................................................................ 21-25 Freescale Semiconductor Contents Title Chapter 21 CDR3 Flash (UC3F) EEPROM MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number xxvii ...

Page 28

... CALRAM Module Configuration Register (CRAMMCR) .................................... 22-13 22.5.2 CALRAM Region Base Address Registers (CRAM_RBAx) ................................ 22-15 22.5.3 CALRAM Overlay Configuration Register (CRAM_OVLCR) ............................. 22-17 22.5.4 CALRAM Ownership Trace Register (CRAM_OTR) ........................................... 22-17 Freescale Semiconductor Contents Title Chapter 22 CALRAM Operation MPC561/MPC563 Reference Manual, Rev. 1.2 Page ...

Page 29

... Running in Debug Mode .................................................................................... 23-27 23.3.1.6 Exiting Debug Mode ........................................................................................... 23-28 23.4 Development Port ....................................................................................................... 23-28 23.4.1 Development Port Pins ........................................................................................... 23-28 23.4.2 Development Serial Clock ...................................................................................... 23-29 23.4.3 Development Serial Data In .................................................................................... 23-29 Freescale Semiconductor Contents Title Chapter 23 Development Support MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number xxix ...

Page 30

... Breakpoint Address Register (BAR) ...................................................................... 23-53 23.6.13 Development Port Data Register (DPDR) .............................................................. 23-53 24.1 Features Summary ........................................................................................................ 24-1 24.1.1 Functional Block Diagram ........................................................................................ 24-2 24.2 Modes of Operation ...................................................................................................... 24-3 24.2.1 Reset Configuration .................................................................................................. 24-3 Freescale Semiconductor Contents Title Chapter 24 READI Module MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number xxx ...

Page 31

... Non-Temporal Ordering of Transmitted Messages ............................................ 24-33 24.7.6 READI Reset Configuration ................................................................................... 24-34 24.7.7 READI Signals ....................................................................................................... 24-36 24.7.7.1 Reset Configuration for Debug Mode ................................................................ 24-36 24.7.7.2 Reset Configuration for Non-Debug Mode ........................................................ 24-37 Freescale Semiconductor Contents Title MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number xxxi ...

Page 32

... Relative Addressing ............................................................................................ 24-54 24.9.3 Queue Overflow Data Trace Error Message ........................................................... 24-54 24.9.4 Data Trace Operation .............................................................................................. 24-54 24.9.5 Data Trace Windowing ........................................................................................... 24-56 24.9.6 Special L-Bus Cases ............................................................................................... 24-56 24.9.7 Data Trace Queuing ................................................................................................ 24-56 Freescale Semiconductor Contents Title MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number xxxii ...

Page 33

... Ownership Trace ........................................................................................................ 24-74 24.13.1 Ownership Trace Messaging .................................................................................. 24-75 24.13.2 Queue Overflow Ownership Trace Error Message ................................................. 24-75 24.13.2.1 OTM Flow .......................................................................................................... 24-75 24.13.2.2 OTM Queueing ................................................................................................... 24-76 24.13.3 OTM Timing Diagrams .......................................................................................... 24-76 Freescale Semiconductor Contents Title MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number xxxiii ...

Page 34

... MPC561/MPC563 Restrictions .................................................................................. 25-32 25.2.1 Non-Scan Chain Operation ..................................................................................... 25-32 25.2.2 BSDL Description ................................................................................................... 25-33 MPC562/MPC564 Compression Features A.1 ICDU Key Features ........................................................................................................ A-1 A.2 Class-Based Compression Model Main Principles......................................................... A-1 xxxiv Contents Title Chapter 25 Appendix A MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number Freescale Semiconductor ...

Page 35

... Show Cycles in Decompression On Mode ....................................................... A-15 A.3.2 Vocabulary Table Storage Operation ........................................................................ A-16 A.3.3 READI Compression ................................................................................................ A-16 A.3.3.1 I-Bus Support Control Register (ICTRL) ............................................................. A-16 A.4 Decompressor Class Configuration Registers (DCCR0-15) ........................................ A-18 Freescale Semiconductor Contents Title MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number xxxv ...

Page 36

... Read/Write Timers and Pin TPU3 Function (RWTPIN) .............................................. D-51 D.20 Serial Input/Output Port (SIOP) ................................................................................... D-53 D.20.1 Parameters................................................................................................................. D-53 xxxvi Contents Title Appendix B Internal Memory Map Appendix C Clock and Board Guidelines Appendix D TPU3 ROM Functions MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number Freescale Semiconductor ...

Page 37

... F.10 AC Timing ..................................................................................................................... F-18 F.10.1 Debug Port Timing .................................................................................................... F-43 F.11 READI Electrical Characteristics .................................................................................. F-45 F.12 RESET Timing............................................................................................................... F-47 F.13 IEEE 1149.1 Electrical Characteristics.......................................................................... F-50 Freescale Semiconductor Contents Title Appendix E Memory Access Timing Appendix F Electrical Characteristics MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number ...

Page 38

... Keep-Alive RAM...................................................................................................... G-18 G.11 AC Timing .................................................................................................................... G-18 G.11.1 Debug Port Timing ................................................................................................... G-41 G.12 READI Electrical Characteristics ................................................................................. G-43 G.13 RESET Timing.............................................................................................................. G-44 G.14 IEEE 1149.1 Electrical Characteristics......................................................................... G-47 xxxviii Contents Title Appendix G 66-MHz Electrical Characteristics MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number Freescale Semiconductor ...

Page 39

... MPWMSM Timing Characteristics .......................................................................... G-60 G.21.2 MMCSM Timing Characteristics ............................................................................. G-62 G.21.3 MDASM Timing Characteristics.............................................................................. G-64 G.22 MPIOSM Timing Characteristics ................................................................................. G-67 G.23 Pin Summary ................................................................................................................ G-68 G.23.1 Package Diagrams..................................................................................................... G-78 G.23.1.1 MPC561/MPC563 Ball Map ................................................................................ G-81 Freescale Semiconductor Contents Title MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number xxxix ...

Page 40

... Paragraph Number xl Contents Title MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number Freescale Semiconductor ...

Page 41

... MPC561/MPC563 Memory Map ........................................................................................... 4-17 4-7 BBC Module Configuration Register (BBCMCR)................................................................. 4-19 4-8 Region Base Address Register (MI_RBA[0:3]) ..................................................................... 4-21 4-9 Region Attribute Register (MI_RA0[0:3]) ............................................................................. 4-22 4-10 Global Region Attribute Register (MI_GRA) ........................................................................ 4-23 Freescale Semiconductor Figures Title MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number xli ...

Page 42

... Real-Time Clock Status and Control Register (RTCSC) ....................................................... 6-43 6-36 Real-Time Clock Register (RTC) ........................................................................................... 6-43 6-37 Real-Time Clock Alarm Register (RTCAL) .......................................................................... 6-44 6-38 Periodic Interrupt Status and Control Register (PISCR) ........................................................ 6-44 xlii Figures Title MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number Freescale Semiconductor ...

Page 43

... Single Beat Read Cycle – Basic Timing – One Wait State .................................................... 9-11 9-7 Basic Flow Diagram of a Single Beat Write Cycle ................................................................ 9-12 9-8 Single Beat Basic Write Cycle Timing – Zero Wait States .................................................... 9-13 Freescale Semiconductor Figures Title MPC561/MPC563 Reference Manual, Rev. 1.2 Page ...

Page 44

... Memory Controller Block Diagram........................................................................................ 10-2 10-3 MPC561/MPC563 Simple System Configuration .................................................................. 10-3 10-4 Bank Base Address and Match Structure ............................................................................... 10-4 10-5 A 4-2-2-2 Burst Read Cycle (One Wait State Between Bursts) ............................................. 10-9 xliv Figures Title MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number Freescale Semiconductor ...

Page 45

... Interrupt Synchronizer Block Diagram................................................................................... 12-6 12-7 UIMB Module Configuration Register (UMCR) ................................................................... 12-7 12-8 Pending Interrupt Request Register (UIPEND)...................................................................... 12-9 13-1 QADC64E Block Diagram ..................................................................................................... 13-1 13-2 QADC64E Conversion Queue Operation............................................................................... 13-5 Freescale Semiconductor Figures Title MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number xlv ...

Page 46

... CCW Priority Situation 11.................................................................................................... 13-61 13-38 CCW Freeze Situation 12 ..................................................................................................... 13-61 13-39 CCW Freeze Situation 13 ..................................................................................................... 13-62 13-40 CCW Freeze Situation 14 ..................................................................................................... 13-62 13-41 CCW Freeze Situation 15 ..................................................................................................... 13-62 13-42 CCW Freeze Situation 16 ..................................................................................................... 13-62 xlvi Figures Title MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number Freescale Semiconductor ...

Page 47

... QADC64E Queue Operation With Pause ............................................................................. 14-40 14-23 QADC64E Clock Subsystem Functions ............................................................................... 14-49 14-24 Bus Cycle Accesses .............................................................................................................. 14-52 14-25 CCW Priority Situation 1...................................................................................................... 14-55 14-26 CCW Priority Situation 2...................................................................................................... 14-55 14-27 CCW Priority Situation 3...................................................................................................... 14-56 Freescale Semiconductor Figures Title MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number xlvii ...

Page 48

... QSPI Block Diagram ............................................................................................................ 15-15 15-11 QSPI Control Register 0 (SPCR0)........................................................................................ 15-17 15-12 SPCR1 — QSPI Control Register ........................................................................................ 15-19 15-13 SPCR2 — QSPI Control Register 2 ..................................................................................... 15-20 15-14 SPCR3 — QSPI Control Register 3 ..................................................................................... 15-21 xlviii Figures Title MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number Freescale Semiconductor ...

Page 49

... TouCAN Module Configuration Register (CANMCR) ....................................................... 16-25 16-10 TouCAN Interrupt Configuration Register (CANICR) ........................................................ 16-27 16-11 Control Register 0 (CANCTRL0)......................................................................................... 16-27 16-12 Control Register 1 (CANCTRL1)......................................................................................... 16-28 16-13 Prescaler Divide Register...................................................................................................... 16-29 Freescale Semiconductor Figures Title MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number xlix ...

Page 50

... MPWMSM Pulse Width Register (MPWMPULR).............................................................. 17-58 17-28 MPWMSM Counter Register (MPWMCNTR) .................................................................... 17-58 17-29 MPWMSM Status/Control Register (MPWMSCR)............................................................. 17-58 17-30 MPIOSM 1-Bit Block Diagram ............................................................................................ 17-60 17-31 MPIOSM — Register Organization ..................................................................................... 17-62 l Figures Title MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number Freescale Semiconductor ...

Page 51

... General Purpose Data Out Register (GPDO) ....................................................................... 18-19 18-22 General Purpose Data In Register (GPDI)............................................................................ 18-19 18-23 Short Register (SHORT_REG)............................................................................................. 18-19 18-24 Example of TouCAN Internal Short with SH_TCAN = 0b110............................................ 18-21 18-25 Short Between TPU Channels .............................................................................................. 18-22 Freescale Semiconductor Figures Title MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number li ...

Page 52

... UC3F EEPROM High Voltage Control Register (UC3FCTL) ............................................ 21-11 21-5 PEGOOD Valid Time ........................................................................................................... 21-14 21-6 Shadow Information ............................................................................................................. 21-16 21-7 Hard Reset Configuration Word (UC3FCFIG) .................................................................... 21-16 21-8 512-Kbyte Array Configuration............................................................................................ 21-19 lii Figures Title MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number Freescale Semiconductor ...

Page 53

... Comparator G–H Value Registers (CMPG–CMPH)............................................................ 23-47 23-22 L-Bus Support Control Register 1 (LCTRL) ........................................................................ 23-47 23-23 L-Bus Support Control Register 2 (LCTRL2) ...................................................................... 23-48 23-24 I-Bus Support Control Register (ICTRL) ............................................................................. 23-51 23-25 Breakpoint Address Register (BAR) .................................................................................... 23-53 Freescale Semiconductor Figures Title MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number liii ...

Page 54

... Indirect Branch Synchronization Message Format with Compressed Code (PTSM - 0)................................................................................................................... 24-45 24-31 Indirect Branch Synchronization Message Format with Compressed Code (PTSM = 1).................................................................................................................. 24-45 24-32 Program Trace Full Message Format.................................................................................... 24-46 24-33 Relative Address Generation and Re-Creation ..................................................................... 24-47 liv Figures Title MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number Freescale Semiconductor ...

Page 55

... Download Request Message ................................................................................................. 24-71 24-68 Upload/Download Information Message.............................................................................. 24-72 24-69 Error Message (Invalid Access Opcode) .............................................................................. 24-72 24-70 Watchpoint Message Format ................................................................................................ 24-73 24-71 Error Message (Watchpoint Overrun) Format...................................................................... 24-73 24-72 Watchpoint Message............................................................................................................. 24-74 Freescale Semiconductor Figures Title MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number lv ...

Page 56

... Decompressor Class Configuration Registers1 (DCCR C-1 MPC561/MPC563 Power Distribution Diagram — 2.6 V .......................................................C-3 C-2 Power Distribution Diagram — and Analog .....................................................................C-3 C-3 Crystal Oscillator Circuit ..........................................................................................................C-4 C-4 RC Filter Example ....................................................................................................................C-5 lvi Figures Title MPC561/MPC563 Reference Manual, Rev. 1.2 Number x ) ..................................................... A-19 Freescale Semiconductor Page ...

Page 57

... D-30 RWTPIN Parameters ............................................................................................................. D-52 D-31 Two Possible SIOP Configurations ....................................................................................... D-53 D-32 SIOP Parameters .................................................................................................................... D-55 D-33 SIOP Function Data Transition Example .............................................................................. D-59 F-1 Option A Power-Up Sequence Without Keep-Alive Supply.................................................. F-14 Freescale Semiconductor Figures Title MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number lvii ...

Page 58

... F-37 JTAG Test Clock Input Timing .............................................................................................. F-51 F-38 JTAG Test Access Port Timing Diagram ............................................................................... F-52 F-39 Boundary Scan (JTAG) Timing Diagram............................................................................... F-53 F-40 QSPI Timing – Master, CPHA = 0 ......................................................................................... F-58 lviii Figures Title MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number Freescale Semiconductor ...

Page 59

... Option B Power-Up Sequence With Keep-Alive Supply ...................................................... G-16 G-7 Option B Power-Down Sequence Without Keep-Alive Supply ............................................ G-17 G-8 Option B Power-Down Sequence with Keep-Alive Supply .................................................. G-17 G-9 Generic Timing Examples ..................................................................................................... G-19 G-10 CLKOUT Pin Timing ............................................................................................................ G-25 Freescale Semiconductor Figures Title MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number lix ...

Page 60

... MCPSM Enable to MPWMO Output Pin Rising Edge Timing Diagram ............................. G-61 G-49 MPWMSM Enable To MPWMO Output Pin Rising Edge Timing Diagram ....................... G-62 G-50 MPWMSM Interrupt Flag to MPWMO Output Pin Falling Edge Timing Diagram............. G-62 lx Figures Title MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number Freescale Semiconductor ...

Page 61

... MPC561/MPC563 Ball Map (Black and White, page 1) ...................................................... G-82 G-67 MPC561/MPC563 Ball Map (Black and White, page 2) ...................................................... G-83 G-68 MPC561/MPC563 Ball Map (Black and White, page 3) ...................................................... G-84 G-69 MPC561/MPC563 Ball Map (Black and White, page 4) ...................................................... G-85 Freescale Semiconductor Figures Title MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number lxi ...

Page 62

... Figure Number lxii Figures Title MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number Freescale Semiconductor ...

Page 63

... FPECR Bit Descriptions ......................................................................................................... 3-26 3-17 Instruction Set Summary ........................................................................................................ 3-28 3-18 RCPU Exception Classes........................................................................................................ 3-35 3-19 Exception Vector Offset Table .............................................................................................. 3-36 3-20 Instruction Latency and Blockage .......................................................................................... 3-39 3-21 Floating-Point Exception Mode Encoding ............................................................................. 3-44 Freescale Semiconductor Tables Title MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number lxiii ...

Page 64

... Interrupt Latency Estimation for Three Typical Cases........................................................... 6-16 6-6 Decrementer Time-Out Periods .............................................................................................. 6-18 6-7 SIUMCR Bit Descriptions ..................................................................................................... 6-25 6-8 Debug Pins Configuration ...................................................................................................... 6-27 6-9 General Pins Configuration .................................................................................................... 6-27 6-10 Single-Chip Select Field Pin Configuration ........................................................................... 6-27 lxiv Tables Title MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number Freescale Semiconductor ...

Page 65

... Data Bus Requirements For Read Cycles............................................................................... 9-31 9-3 Data Bus Contents for Write Cycles....................................................................................... 9-32 9-4 Priority Between Internal and External Masters over External Bus ....................................... 9-36 9-5 4 Word Burst Length and Order ............................................................................................. 9-38 Freescale Semiconductor Tables Title MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number lxv ...

Page 66

... QADC64E_A Address Map ................................................................................................... 13-3 13-2 QADC64E_B Address Map.................................................................................................... 13-4 13-3 Multiplexed Analog Input Channels....................................................................................... 13-7 13-4 Analog Input Channels ........................................................................................................... 13-7 13-5 QADCMCR Bit Descriptions ................................................................................................. 13-8 13-6 QADC64E Bus Error Response............................................................................................ 13-11 lxvi Tables Title MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number Freescale Semiconductor ...

Page 67

... QASR0 Bit Descriptions....................................................................................................... 14-22 14-16 Pause Response..................................................................................................................... 14-26 14-17 Queue Status ......................................................................................................................... 14-26 14-18 QASR1 Bit Descriptions....................................................................................................... 14-28 14-19 CCW Bit Descriptions .......................................................................................................... 14-31 14-20 QADC64E_A Multiplexed Channel Assignments and Signal Designations ....................... 14-32 Freescale Semiconductor Tables Title MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number lxvii ...

Page 68

... SCI Pin Functions ................................................................................................................. 15-51 15-29 Serial Frame Formats............................................................................................................ 15-52 15-30 Examples of SCIx Baud Rates.............................................................................................. 15-53 15-31 Effect of Parity Checking on Data Size ................................................................................ 15-53 15-32 QSCI1CR Bit Descriptions ................................................................................................... 15-60 15-33 QSCI1SR Bit Descriptions ................................................................................................... 15-61 lxviii Tables Title MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number Freescale Semiconductor ...

Page 69

... MCPSM Register Address Map ........................................................................................... 17-17 17-7 MCPSMSCR Bit Descriptions ............................................................................................ 17-18 17-8 Clock Prescaler Setting ......................................................................................................... 17-18 17-9 MMCSM Address Map ........................................................................................................ 17-22 17-10 MMCSMCNT Bit Descriptions............................................................................................ 17-23 17-11 MMCSMML Bit Descriptions.............................................................................................. 17-24 Freescale Semiconductor Tables Title MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number lxix ...

Page 70

... PPMPCR Bit Descriptions.................................................................................................... 18-12 18-4 SAMP[0:2] Bit Settings ........................................................................................................ 18-13 18-5 PPMPCR[CM] and PPMPCR[STR] Bit Operation.............................................................. 18-15 18-6 Configuration Register (TX and RX) Channel Settings ....................................................... 18-17 18-7 SHORT_REG Bit Descriptions ............................................................................................ 18-20 lxx Tables Title MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number = 40 MHz.................... 17-38 SYS Freescale Semiconductor ...

Page 71

... UC3F External Interface Signals ............................................................................................ 21-4 21-2 UC3F Register Programming Model ...................................................................................... 21-5 21-3 UC3FMCR Bit Descriptions................................................................................................... 21-6 21-4 UC3FMCRE Bit Descriptions ................................................................................................ 21-9 21-5 UC3FCTL Bit Descriptions .................................................................................................. 21-11 21-6 RCW Bit Descriptions .......................................................................................................... 21-17 Freescale Semiconductor Tables Title MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number lxxi ...

Page 72

... CMPG-CMPH Bit Descriptions ........................................................................................... 23-47 23-24 LCTRL1 Bit Descriptions..................................................................................................... 23-47 23-25 LCTRL2 Bit Descriptions..................................................................................................... 23-49 23-26 ICTRL Bit Descriptions........................................................................................................ 23-51 23-27 ISCT_SER Bit Descriptions ................................................................................................. 23-52 23-28 BAR Bit Descriptions ........................................................................................................... 23-53 Freescale Semiconductor Tables Title MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number lxxii ...

Page 73

... Power Management Mechanism Overview .......................................................................... 24-86 25-1 MPC561 Boundary Scan Bit Definition ................................................................................. 25-5 25-2 MPC563 Boundary Scan Bit Definition ............................................................................... 25-17 25-3 Instruction Decoding............................................................................................................. 25-30 A-1 ICTRL Bit Descriptions......................................................................................................... A-17 Freescale Semiconductor Tables Title MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number lxxiii ...

Page 74

... Array Program and Erase Characteristics ............................................................................... F-12 F-7 CENSOR Cell Program and Erase Characteristics................................................................. F-12 F-8 Flash Module Life................................................................................................................... F-12 F-9 Power Supply Pin Groups....................................................................................................... F-13 F-10 Bus Operation Timing ............................................................................................................ F-20 Freescale Semiconductor Tables Title MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number lxxiv ...

Page 75

... G-15 JTAG Timing ......................................................................................................................... G-47 G-16 QADC64E Conversion Characteristics ................................................................................. G-50 G-17 QSPI Timing .......................................................................................................................... G-52 G-18 QSCI Timing.......................................................................................................................... G-53 G-19 GPIO Timing ......................................................................................................................... G-56 G-20 TPU3 Timing ......................................................................................................................... G-57 G-21 TouCAN Timing.................................................................................................................... G-58 Freescale Semiconductor Tables Title MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number lxxv ...

Page 76

... MCPSM Timing Characteristics............................................................................................ G-60 G-24 MPWMSM Timing Characteristics ....................................................................................... G-60 G-25 MMCSM Timing Characteristics .......................................................................................... G-62 G-26 MDASM Timing Characteristics........................................................................................... G-64 G-27 MPIOSM Timing Characteristics .......................................................................................... G-67 G-28 MPC561/MPC563 Signal Names and Pin Names ................................................................. G-68 lxxvi Tables Title MPC561/MPC563 Reference Manual, Rev. 1.2 Page Number Freescale Semiconductor ...

Page 77

... Chapter 6, “System Configuration and system functions that normally must be provided in external circuits. In addition designed to Freescale Semiconductor Suggested Reading for further information. Features.” Unit,” describes the RISC processor (RCPU) used in the MPC500 Module,” ...

Page 78

... Operation.” The two queued analog-to-digital converter Module.” The MPC561/MPC563 contains one queued Module,” describes the three CAN 2.0B controller modules (MIOS14).” The modular I/O system (MIOS) Module.” The PPM functions as a MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor ...

Page 79

... DC/AC electrical characteristics, and AC timing characteristics of the MPC561/MPC563 at the optional operating frequency of 66 MHz. This document also includes a register index and comprehensive index. Freescale Semiconductor 3,” describes an enhanced version of the original TPU, an (DPTRAM).” The dual-port RAM (DPTRAM) module EEPROM.” The MPC563 U-bus CDR3 (UC3F) EEPROM Operation.” ...

Page 80

... This document uses the following notational conventions: cleared/set When a bit takes the value zero said to be cleared; when it takes a value of one said to be set. lxxx ΤΜ architecture. Also listed are documents that further complement . MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor ...

Page 81

... An active low signal changes from logic level zero to logic level one when negated, and an active high signal changes from logic level one to logic level zero. Notational Conventions Table i contains notational conventions that are used in this document. Freescale Semiconductor MPC561/MPC563 Reference Manual, Rev. 1.2 lxxxi ...

Page 82

... Less = Equal ≥ Equal or greater ≤ Equal or less ≠ Not equal • AND | Inclusive OR (OR) ⊕ Exclusive OR (EOR) Complementation : Concatenation ? Transferred ⇔ Exchanges ± Sign bit; also used to show tolerance « Sign extension Meaning MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor ...

Page 83

... Register used for indicating conditions such as carries and overflows for integer operations References The Sematech Official Dictionary and the Reference Guide to Letter Symbols for Semiconductor Devices by the JEDEC Council/Electronics Industries Association are recommended as references for terminology and symbology. Freescale Semiconductor Meaning MPC561/MPC563 Reference Manual, Rev. 1.2 lxxxiii ...

Page 84

... MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor ...

Page 85

... One queued serial multi-channel module (QSMCM), which contains one queued serial peripheral interface (QSPI) and two serial controller interfaces (SCI/UART) • One peripheral pin multiplexing module (PPM) with a parallel to serial driver Freescale Semiconductor Table 1-1. MPC56x Family Features Flash None None ...

Page 86

... I/O system — 2.6 ± 0.1-V internal logic — <150µA on-chip voltage shunt regulator for RAM standby operation 1.2 Block Diagram Figure 1 block diagram of the MPC561/MPC563. 1-2 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor ...

Page 87

... The MPC561/MPC563 key features are explained in the following sections. 1.3.1 High-Performance CPU System • Fully static design • Four major power saving modes — On, doze, sleep, deep-sleep, and power-down Freescale Semiconductor 512 Kbytes Flash MPC563 only Burst Buffer U-Bus READI L2U ...

Page 88

... Support for enhanced exception table relocation feature • Branch target buffer • Contains 2 Kbytes of decompression RAM (DECRAM) for code compression. This RAM may also be used as general-purpose RAM when the code compression feature is not used. 1-4 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor ...

Page 89

... External 4.75- to 5.25-V VFLASH power supply for program, erase, and read operations • Security modes for software protection • Typical endurance of 100,000 write/erase cycles @ 25ºC • Typical data retention of 100 years @ 25ºC Freescale Semiconductor MPC561/MPC563 Reference Manual, Rev. 1.2 Overview 1-5 ...

Page 90

... Each TPU3 is a micro-coded timer subsystem • 8 Kbytes of dual port TPU RAM (DPTRAM) shared by two TPU3 modules for TPU micro-code 1.3.3.2 22-Channel Modular I/O System (MIOS14) • Six modulus counter sub-modules (MCSM) • 10 double-action sub-modules (DASM) 1-6 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor ...

Page 91

... Open network architecture, multi-master concept — High immunity to EMI — Short latency time for high-priority messages — Low-power sleep mode, with programmable wake-up on bus activity — TouCAN_C pins are shared with MIOS14 GPIO or QSMCM Freescale Semiconductor MPC561/MPC563 Reference Manual, Rev. 1.2 Overview 1-7 ...

Page 92

... Software configurable clock (TCLK) based on system clock • Software selectable clock modes (SPI mode and TDM mode) • Software selectable operation modes — Continuous mode — Start-transmit-receive (STR) mode • Software configurable internal modules interconnect (shorting) 1-8 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor ...

Page 93

... CPU Core BBC L2U SRAM Flash (2 modules, 256-Kbyte and 192-Kbyte) USIU JTAG READI UIMB QADC64E QSMCM MIOS Freescale Semiconductor MPC555 Identical Basic Enhanced Code Compression (classes scheme Identical 26 Kbytes 448-Kbyte CMF 512-Kbyte UC3F (1 module) on MPC563 only. Basic Selectable by RCW None Identical ...

Page 94

... READI — New module • USIU — Enhanced interrupt controller — ENGCLK default frequency 1-10 MPC555 (2) Identical (3) (2) Identical (2) (6 Kbytes) Identical (8 Kbytes) — MPC561/MPC563 Reference Manual, Rev. 1.2 MPC561/MPC563 New Module Freescale Semiconductor ...

Page 95

... MPC561/MPC563 Address Map The internal memory map is organized as a single 4-Mbyte block. The user can assign this block to one of eight locations by programming a register in the USIU (IMMR[ISB]). The eight possible locations are the Freescale Semiconductor 1-2. To Battery R To IRAMSTBY Pad ...

Page 96

... USIU and Flash control registers (16-Kbytes) — UIMB interface and IMB3 modules (32-Kbytes) — CALRAM/READI control registers (256-bytes) 1-12 Figure 1-3. MPC561/MPC563 Memory Map MPC561/MPC563 Reference Manual, Rev. 1.2 Figure 1-3). The Internal 4-Mbyte Memory Block (Can reside in one of eight locations) Figure 1-4. Freescale Semiconductor ...

Page 97

... Kbytes 0x3F 7FFF 0x3F 8000 CALRAM 32 Kbytes 0x3F F000 4-Kbyte Overlay Section 0x3F FFFF Note: Flash is available only on the MPC563/MPC564. Freescale Semiconductor MPC561/MPC563 Reference Manual, Rev. 1.2 0x2F C000 USIU Control Registers 0x2F C800 UC3F Control Registers* 0x2FC80B Reserved 0x30 0000 ...

Page 98

... This list contains references to currently available and planned documentation. • MPC555 User’s Manual (MPC555UM/AD) • RCPU Reference Manual (RCPURM/AD) • Nexus Standard Specification (non-Freescale document) available at: http://www.nexus5001.org/ • IEEE 1149.1 Specification (non-Freescale document) 1-14 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor ...

Page 99

... Refer to Appendix F, “Electrical for detailed electrical information for each signal. 2.1 Signal Groupings Figure 2-1 illustrates the external signals of the MPC561/MPC563 grouped by functional module. Freescale Semiconductor NOTE Characteristics,” and Appendix G, “66-MHz Electrical MPC561/MPC563 Reference Manual, Rev. 1.2 Characteristics,” 2-1 ...

Page 100

... MIOS and QSMCM) UC3F Flash 1 EEPROM 5 Pins System Control 3 Pins JTAG/BDM/READI 5 Pins MIOS14 34 Pins TPU3 A and B 34 Pins Note: In cases where one multiplexed signal is an input and another is an output, together they are shown as I/O. 1 The MPC561 has no Flash EEPROM Freescale Semiconductor ...

Page 101

... TSIZ[0:1] 2 RD/WR 1 BURST 1 BDIP Freescale Semiconductor Function after Type 1 Reset Bus Interface Address Bus [8:31]. Specifies the physical address of the I/O Controlled by bus transaction. The address is driven onto the bus and kept RCW[SC]. valid until a transfer acknowledge is received from the slave. ...

Page 102

... Special Transfer Start. This output signal is driven by the O MPC561/MPC563 to indicate the start of a transaction on the external bus or signals the beginning of an internal transaction in show cycle mode. MPC561/MPC563 Reference Manual, Rev. 1.2 Description Freescale Semiconductor ...

Page 103

... IRQ0 / SGPIOC0 / MDO4 IRQ1 / RSV / SGPIOC1 1 IRQ2 / CR / SGPIOC2 / 1 2 MTS IRQ3 / KR / RETRY / SGPIOC3 1 Freescale Semiconductor Function after Type 1 Reset Interrupt Controller Interrupt Request 0. One of the eight external signals that I can request, by means of the internal interrupt controller, a MDO4 if the service routine from the RCPU. IRQ0 is a non-maskable Nexus (READI) interrupt (NMI) ...

Page 104

... Address Type [0:3]. Indicates one of the 16 address types to O which the address applies. The address type signals are valid at the rising edge of the clock in which the special transfer start (STS) is asserted. MPC561/MPC563 Reference Manual, Rev. 1.2 Description Table 10-8. Freescale Semiconductor ...

Page 105

... HRESET 1 SRESET 1 SGPIOC6 / FRZ / PTR 1 SGPIOC7 / IRQOUT/ LWP0 1 Freescale Semiconductor Function after Type 1 Reset System Control Power-On Reset. This signal should be activated as a result of a voltage failure on the keep-alive power supply. The I signal has a glitch detector to ensure that low spikes of less PORESET / than 20 ns are rejected ...

Page 106

... They report the number of instructions flushed from the history buffer in the RCPU. See Chapter 23, “Development MPC561/MPC563 Reference Manual, Rev. 1.2 Description Chapter 23, Support,” for more details. Chapter 23, Support,” for more details. Support,” for details. Freescale Semiconductor ...

Page 107

... Signals TMS / EVTI 1 TDI / DSDI / MDI0 1 TCK / DSCK / MCKI 1 TDO / DSDO / MDO0 1 JCOMP / RSTI 1 Freescale Semiconductor Function after Type 1 Reset JTAG/BDM/READI I TMS unless the Test Mode Select. This input controls test mode operations Nexus (READI) for on-board test logic (JTAG). port is enabled, EVTI ...

Page 108

... TouCAN O A_CNTX0 TouCAN_A Transmit Data. This signal is the serial data output. I A_CNRX0 TouCAN_A Receive Data. This signal is the serial data input. O B_CNTX0 TouCAN_B Transmit Data. This signal is the serial data output. MPC561/MPC563 Reference Manual, Rev. 1.2 Description Freescale Semiconductor ...

Page 109

... VFLASH 1 4 VDDF 1 4 VSSF 1 ETRIG[1:2] / PCS[6:7] 2 A_AN0 / A_ANw / A_PQB0 1 A_AN1 / A_ANx/ A_PQB1 1 Freescale Semiconductor Function after Type 1 Reset I B_CNRX0 TouCAN_B Receive Data. This signal is the serial data input. 4 UC3F Flash EPEE. This external program/erase enable control signal I EPEE externally controls the program or erase operations. When held low, program or erase operations on the entire internal Flash module are disabled ...

Page 110

... Analog Channel 0. Internally multiplexed input-only analog channel. Passed separate signal to the QADC64E. I Multiplexed Analog Input (B_ANw). Externally multiplexed B_AN0 analog input. Port B_PQB0. This is a bidirectional general-purpose I/O if I/O the QADC64E is configured in enhanced mode, otherwise input only. MPC561/MPC563 Reference Manual, Rev. 1.2 Description Freescale Semiconductor ...

Page 111

... B_AN[48:51] / B_PQB[4:7] 4 B_AN[52:54] / B_MA[0: B_PQA[0:2] B_AN[55:59] / B_PQA[3:7] 5 VRH 1 VRL 1 Freescale Semiconductor Function after Type 1 Reset I Analog Channel 1. Internally multiplexed input-only analog channel. Passed separate signal to the QADC64E. I Multiplexed Analog Input (B_ANx). Externally multiplexed B_AN1 analog input. Port B_PQB1. This is a bidirectional general-purpose I/O if ...

Page 112

... Port QGPO 1. When these signals are not needed for SCI applications, they can be configured as general-purpose QGPO1 O outputs. When the transmit enable bit in the SCI control register is set to a logic 1, these signals cannot function as general-purpose outputs. MPC561/MPC563 Reference Manual, Rev. 1.2 Description Freescale Semiconductor ...

Page 113

... RXD1 / QGPI1 1 6 RXD2 / QGPI2 / C_CNRX0 1 MDA[11:15, 27:31] 10 MPWM0 / MDI1 1 Freescale Semiconductor Function after Type 1 Reset O Transmit Data 2. This is the serial data output from the SCI2 Port QGPO 2. When this signal is not needed for SCI applications it can be configured as general-purpose output. O When the transmit enable bit in the SCI control register is set ...

Page 114

... MMCSM24 READI Message Data Out. Message data out (MDO[6:7]) are output signals used for uploading OTM, BTM, DTM, and O read/write accesses. External latching of MDO occurs on rising edge of MCKO. Eight MDO signals are implemented. MPC561/MPC563 Reference Manual, Rev. 1.2 Description Freescale Semiconductor ...

Page 115

... Table 2-1. MPC561/MPC563 Signal Descriptions (continued) No. of Signal Name Signals MPIO32B0 / VF0 / MDO1 1 MPIO32B1 / VF1 / MCKO 1 MPIO32B2 / VF2 / MSEI 1 Freescale Semiconductor Function after Type 1 Reset I/O MIOS14 GPIO 0. Allows the signals to be used as general-purpose inputs/outputs. Visible Instruction Queue Flush Status 0. These signals MPIO32B0 ...

Page 116

... MIOS14 GPIO 11. This function allows the signals to be MPIO32B11 used as general-purpose inputs/outputs. I TouCAN_C Receive Data. This is the serial data input signal for the TouCAN_C module. MPC561/MPC563 Reference Manual, Rev. 1.2 Description Chapter 23, Support,” for details. Chapter 23, Support,” for details. Freescale Semiconductor ...

Page 117

... B_T2CLK / PCS4 1 NVDDL 1 QVDDL 1 VDDH 1 VDD 1 KAPWR 1 Freescale Semiconductor Function after Type 1 Reset I/O MIOS14 GPIO 12. This function allows the signals to be MPIO32B12 used as general-purpose inputs/outputs. O TouCAN_C Transmit Data. This is the serial data output signal for the TouCAN_C module. I/O MIOS14 GPIO 13. This function allows the signals to be MPIO32B13 used as general-purpose inputs/outputs ...

Page 118

... READI submodule shared with MIOS14 GPIO MIOS14 PWM submodule shared with MIOS14 GPIO Debug pins shared with MIOS14 GPIO and READI PPM submodule shared with MIOS14 GPIO PPM submodule shared with MIOS14 PWM submodule MPC561/MPC563 Reference Manual, Rev. 1.2 Description Freescale Semiconductor ...

Page 119

... MPIO32B6 / MPWM4 / MDO6 MPWM18/MDO6 MPWM19/MDO7 1 The MDO6 bit in the PDMCR2 register determines where the MDO6 signal is available. Freescale Semiconductor Module Sharing READI submodule shared with MIOS14 PWM submodule TPU3 modules shared with QSMCM module. QADC64E modules shared with QSMCM module. Functionality in Reduced ...

Page 120

... PRDS SPRDS T2CLK_PU 0000_0000_0000_0000 0x2F C03C — 0000_0000_0000_0000 Table 2-5. PDMCR Field Descriptions Description Appendix F, “Electrical Appendix F, “Electrical Characteristics.” Characteristics.” MPC561/MPC563 Reference Manual, Rev. 1.2 Characteristics.” The PULL_DIS — LSB Characteristics.” Appendix F, “Electrical Appendix F, Appendix F, Freescale Semiconductor ...

Page 121

... MSB Field PREDIS_ EN — HRESET Addr Field PPMV — HRESET Figure 2-3. Pads Module Configuration Register 2 (PDMCR2) Freescale Semiconductor Description for more information on PRDS. for more information on SPRDS TCNC MPI7 MPI8 MPI9 0000_0000_0000_0000 0x2F C038 19 20 ...

Page 122

... This bit will be disabled if full port mode is enabled in the READI module, and MDO6 bit is logic ‘0’. 22:24 — Reserved 25 PCSV Selects the polarity of QSMCM module QSPI PCS signals in the PCS expanded mode. 0 Selects Active High. 1 Selects Active Low. 2-24 Table 2-6. PDMCR2 Field Description Description 2-8. MPC561/MPC563 Reference Manual, Rev. 1.2 Table 2-7. Freescale Semiconductor ...

Page 123

... MPIO32B14 001 MPIO32B14 010 PPM_RX0 011 PPM_RX0 101 MPIO32B14 110 PPM_RX0 111 PPM_RX0 PCS_IN[3:0] 0000 0001 Freescale Semiconductor Description Table 2-7. TCNC Pad Functionalities RXD2/QGPI2/ C_CNRX0 RXD2/QGPI2 MPIO32B11 RXD2/QGPI2 C_CNRX0 C_CNRX0 MPIO32B11 Table 2-8. PPMPAD Pad Functionalities MPIO32B15/ MPWM3/ MPWM2/ PPM_TX0 ...

Page 124

... A_T2CLK PCS4 MPC561/MPC563 Reference Manual, Rev. 1.2 PCS_OUT[7:0] IF PCSV = 1 11111011 11110111 11101111 11011111 10111111 01111111 11111111 RESERVED A_T2CLK internal B_T2CLK internal TPU_A TPU_B Connection Connection A_T2CLK/PCS5 B_T2CLK/PCS4 Pad Pad A_T2CLK/PCS5 A_T2CLK/PCS5 Pad Pad A_T2CLK/PCS5 B_T2CLK Signal Pad driven HI internally Freescale Semiconductor ...

Page 125

... ETRIG1/PCS6 and ETRIG2/PCS7 pads dependent on the values of PDMCR2[PCS6EN], PDMCR2[PCS7EN], SHORT_REG [SH_ET1] and SHORT_REG [SH_ET2]. Also shown in this table is the internal connection of the ETRIG signals when the enhanced chip select function is used. Freescale Semiconductor A_T2CLK/PCS5 B_T2CLK/PCS4 PAD Function ...

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... Disabled A_TPUCH15 B_TPUCH15 PCS7 Enabled PCS6 PCS7 Enabled A_TPUCH15 B_TPUCH15 PCS7 Disabled PCS6 PCS7 Disabled A_TPUCH15 B_TPUCH15 BDM READI 0 RSTI DSCK MCKI DSDI MDI0 DSDO MDO0 — EVTI Freescale Semiconductor ETRIG2 internal connection ETRIG2 ETRIG2 PCS7 PCS7 ETRIG2 ETRIG2 PCS7 PCS7 ...

Page 127

... READI module will be held inactive since only one of the multiplexed functions JCOMP and RSTI can be asserted at the negation of PORESET/TRST). JTAG mode is exited by: • Drive JCOMP/RSTI low. PORESET/TRST and analog signals ANx, EXTAL, XTAL, and TDI/TDO/TMS/TCK are not in the JTAG scan path. Freescale Semiconductor State When Sampled BDM Mode High SRESET negation Low ...

Page 128

... Both of these should be done at least 4 clocks before driving JCOMP/RSTI high 2-30 JTAG On Figure 2-4. Debug Mode Selection (JTAG) Figure 2-5 Configure BDM Enable Nexus Figure 2-5. Debug Mode Selection (BDM) MPC561/MPC563 Reference Manual, Rev. 1.2 T JTAG Disabled for BDM mode selection. T BDM On Nexus Off Figure 2-6 Freescale Semiconductor ...

Page 129

... The function of many signals depends upon the value latched. If the value on the data bus changes, then the function of various signals may also change. This is especially true if the reset configuration word (RCW) comes from the Flash, because the Flash does not drive the RCW until 256 clocks after the start of Freescale Semiconductor Enable and Configure Nexus Figure 2-6 ...

Page 130

... For the signals that support debug, opcode tracking, and bus control functionality, the pull resistors will be controlled by the SPRDS bit in the PDMCR register. During reset this signal will be synchronously used 2-32 Table 2-14. NOTE MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor ...

Page 131

... Do not connect 2.6-V outputs to a driver or pull-up greater than 3.1 V. Depending on the application, pins may require a pull-down resistor to avoid getting any command due to noise. Freescale Semiconductor NOTE NOTE MPC561/MPC563 Reference Manual, Rev. 1.2 Signal Descriptions Section 2.3, “ ...

Page 132

... Controlled by SC bit in the reset config word. See Table 6-10 Controlled by SC bit in the reset config word. See Table 6-10. No Yes MDO4 if the Nexus (READI) port is enabled, IRQ0 Yes otherwise. See Section 2.5. Yes Yes IRQ1 Yes Yes Yes IRQ2 Yes IRQ3 Freescale Semiconductor ...

Page 133

... V 11 MODCK1 2 IRQ[6: MODCK[2:3] 2.6 V PULL_SEL TSIZ[0:1] 2 RD/WR 2 BURST 2 BDIP 2.6 V 7,12 TS 2.6 V Freescale Semiconductor Drive Load Reset State 2 (pF until reset 6, 8 negates until reset 6, 8 negates 5 Yes until PRDS is set No NA PU2.6 until reset negates PU2.6 until PRDS is set ...

Page 134

... Function After HRESET, s PORESET/TRST Enabled TEA RSTCONF until reset negates Controlled by DBGC in the reset configuration word. No See Table 6-8. No CS[0:3] No Controlled by bit ATWC (bit 12) of the reset configuration No word. See Table 6-8. No Yes PORESET/TRST Yes Yes HRESET Yes SRESET Freescale Semiconductor ...

Page 135

... IWP3 2 IWP[0: VFLS[0:1] 2.6 V TMS / 2.6 V EVTI 2.6 V TDI / 2.6 V DSDI / 2.6 V MDI0 2.6 V TCK / 2.6 V DSCK / 2.6 V MCKI 2.6 V Freescale Semiconductor Drive Load Reset State 2 (pF) 5 Yes until PRDS is set until reset negates until reset negates 5 Yes until PRDS is set No 50 ...

Page 136

... MPC561/MPC563 Reference Manual, Rev. 1.2 Hysteresi Function After HRESET, s PORESET/TRST Enabled? No DSDO unless the Nexus (READI) port (MDO0 JTAG mode (TDO) is enabled. See Section 2. See Section 2. XTAL NA EXTAL NA XFC No CLKOUT No EXTCLK No ENGCLK (2 QGPO0 QGPIO[1: QGPIO4 No No QGPIO5 No No QGPIO6 No No QGPO1 No Freescale Semiconductor ...

Page 137

... MDI1 2 MPWM1 / 5 V MDO2 2 MPWM2 / 5 V 2.6 V PPM_TX1 5 V MPWM3 PPM_RX1 2.6 V MPWM16 MPWM17 / 5 V MDO3 2.6 V Freescale Semiconductor Drive Load Reset State 2 (pF) Yes PU5 until PULL_DIS1 is Yes set Yes Must be driven or connected pull device NA NA Must be driven or connected to NA ...

Page 138

... MSEO. See Section 2.5. No Yes MPIO32B4 No Yes MPIO32B5 unless the Nexus (READI) port is enabled, then No MDO5. See Section 2.5. Yes MPIO32B6 unless the Nexus (READI) port is enabled, then Yes MDO6. See Section 2.5. No Yes MPIO32B[7:9] Yes Yes MPIO32B10 No Yes MPIO32B11 No Freescale Semiconductor ...

Page 139

... V A_TPUCH[0: A_T2CLK / 5 V PCS5 5 V B_TPUCH[0: B_T2CLK / 5 V PCS4 5 V ETRIG[1: PCS[6: A_AN0 / 5 V A_ANw / 5 V A_PQB0 5 V Freescale Semiconductor Drive Load Reset State 2 (pF) 5 Yes PU5 until PULL_DIS0 is Yes set 5 Yes Pull device enabled until PULL_DIS0 is 16 set Yes 50 ...

Page 140

... PU5 when driver not enabled or Yes NA until PULL_DIS2 is 5 Yes set MPC561/MPC563 Reference Manual, Rev. 1.2 Hysteresi Function After HRESET, s PORESET/TRST Enabled? No A_AN1 No Yes No A_AN2 No Yes No A_AN3 No Yes No A_AN[48:51] Yes No A_AN[52:54] Yes Yes No A_AN[55:59] Yes No B_AN0 No Yes No B_AN1 No Yes No B_AN2 No Yes Freescale Semiconductor ...

Page 141

... V A_CNTX0 5 V B_CNTX0 5 V A_CNRX0 5 V B_CNRX0 EPEE 2 B0EPEE 2 VFLASH VDDF 2 VSSF 0 V Freescale Semiconductor Drive Load Reset State 2 (pF) Yes NA PU5 when driver not enabled or Yes NA until PULL_DIS2 is 5 Yes set Yes NA PU5 when driver not enabled or 5 Yes 50 ...

Page 142

... MPC561/MPC563 Reference Manual, Rev. 1.2 Hysteresi Function After HRESET, s PORESET/TRST Enabled? — NVDDL — VDDH — VDDI — VSS — KAPWR — IRAMSTBY — QVDDL — VDDSYN — VSSSYN — VRH — VRL — ALTREF — VDDA — VSSA Freescale Semiconductor ...

Page 143

... For this 5-V output, a drive load of 200 pf is possible, but will have a rise/fall time of 100ns. 18 MPC563 only, no connection on MPC561. 19 IRAMSTBY is the input to an approximately 1.7V voltage regulator. It should be connected through a resistor to a standby power supply. Freescale Semiconductor MPC561/MPC563 Reference Manual, Rev. 1.2 Signal Descriptions 2-45 ...

Page 144

... Signal Descriptions 2-46 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor ...

Page 145

... This section provides an overview of the RCPU. For a detailed description of this processor, refer to the RCPU Reference Manual. The following sections describe each block and sub-block. 3.1 RCPU Block Diagram Figure 3-1 provides a block diagram of the RCPU. Freescale Semiconductor MPC561/MPC563 Reference Manual, Rev. 1.2 3-1 ...

Page 146

... Load/Store Floating Data Write Back Bus 2 slots/clock Figure 3-1. RCPU Block Diagram MPC561/MPC563 Reference Manual, Rev. 1.2 FPU FPR History FPR (32 X 64) Load/ Store Integer Data Load/ Store Address ALU/ BFU IMUL/ IDIV GPR History GPR (32 X 32) Control Regs Freescale Semiconductor ...

Page 147

... Instructions issued beyond a predicted branch do not complete execution until the branch is resolved, preserving the programming model of sequential execution. If branch prediction is incorrect, the instruction unit flushes all predicted path instructions, and instructions are issued from the correct path. Freescale Semiconductor (FPU),” or refer to the RCPU Reference Manual. MPC561/MPC563 Reference Manual, Rev. 1.2 ...

Page 148

... Figure 3-2. Sequencer Data Path Table 3-1. RCPU Execution Units Description Includes the implementation of all branch instructions. Includes implementation of all load and store instructions, whether defined as part of the integer processor or the floating-point processor. MPC561/MPC563 Reference Manual, Rev. 1.2 32 Instruction Buffer 32 Instruction Pre-fetch Queue 32 Freescale Semiconductor ...

Page 149

... IMUL–IDIV and ALU–BFU are implemented as separate execution units. The ALU–BFU unit can execute one instruction per clock cycle. IMUL–IDIV instructions require multiple clock cycles to execute. IMUL–IDIV is pipelined for multiply instructions, so that consecutive multiply instructions can be issued Freescale Semiconductor Description Includes implementation of all integer instructions except load/store instructions. ...

Page 150

... Virtual environment architecture (VEA) — describes the memory model for a multiprocessor environment, and describes other aspects of virtual environments. Implementations that conform to the VEA also adhere to the UISA, but may not necessarily adhere to the OEA. 3-6 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor ...

Page 151

... Registers can be accessed explicitly through specific instructions such as move to special-purpose register (mtspr) or move from special-purpose register (mftspr), or implicitly as part of an instruction’s execution. Some registers are accessed both explicitly and implicitly. Freescale Semiconductor MPC561/MPC563 Reference Manual, Rev. 1.2 Central Processing Unit 3-7 ...

Page 152

... SUPERVISOR MODEL OEA Machine State Register 0 Supervisor-Level SPRs 63 See Table 3-2 supervisor-level SPRs Development Support SPRs See Table 3-3 development-support SPRs Figure 3-3. RCPU Programming Model MPC561/MPC563 Reference Manual, Rev. 1.2 MSR 31 for list of 31 for list of 31 Freescale Semiconductor ...

Page 153

... Freescale Semiconductor Chapter 11, “L-Bus to U-Bus Interface Table 3-2. Supervisor-Level SPRs Special-Purpose Register DAE/Source Instruction Service Register (DSISR) See Section 3.9.2, “DAE/Source Instruction Service Register (DSISR),” for bit descriptions. Data Address Register (DAR) See Section 3.9.3, “Data Address Register descriptions ...

Page 154

... L2U Region Attribute Register 0 (L2U_RA0) See Table 11-9 for bit descriptions. L2U Region Attribute Register 1 (L2U_RA1) See Table 11-9 for bit descriptions. L2U Region Attribute Register 2 (L2U_RA2) See Table 11-9 for bit descriptions. MPC561/MPC563 Reference Manual, Rev. 1 See 1 . See 1 . See 1 . See Freescale Semiconductor ...

Page 155

... Freescale Semiconductor Special-Purpose Register L2U Region Attribute Register 3 (L2U_RA3) See Table 11-9 for bit descriptions. Floating-Point Exception Cause Register (FPECR) See Section 3.9.10.2, “Floating-Point Exception Cause Register (FPECR),” for bit descriptions. ...

Page 156

... Table 23-28 for bit descriptions. Development Port Data Register (DPDR) See Section 23.6.13, “Development Port Data Register (DPDR),” for bit descriptions. Section 3.7.5, “Integer Exception Register GPR0 GPR1 . . . . . . GPR31 Unchanged MPC561/MPC563 Reference Manual, Rev. 1.2 1 (continued) (XER).” Freescale Semiconductor LSB 31 ...

Page 157

... FPSCR are sticky status bits, which are normal status bits, and which are control bits. [0], [3:12], [21:23] FEX and VX are the logical ORs of other FPSCR bits. Therefore these two bits are not listed among the FPSCR bits directly affected by the various instructions. Freescale Semiconductor Section 3.7.4, “Condition Register FPR0 FPR1 . . . ...

Page 158

... Table 3-5. Table 3-5. FPSCR Bit Descriptions Description MPC561/MPC563 Reference Manual, Rev. 1 FPRF0 Sticky bit Not sticky Not sticky Sticky bit Sticky bit Sticky bit Sticky bit Sticky bit Sticky bit Sticky bit Sticky bit Sticky bit Freescale Semiconductor 15 LSB 31 RN ...

Page 159

... Floating-point underflow exception enable. This bit should not be used to determine whether denormalization should be performed on floating-point stores Floating-point zero divide exception enable Floating-point inexact exception enable. Freescale Semiconductor Description MPC561/MPC563 Reference Manual, Rev. 1.2 Central Processing Unit Sticky bit Not sticky Not sticky Not sticky Table 3-6 for specific bit — ...

Page 160

... Normalized number 11000 – Denormalized number 10010 – Zero 00010 + Zero 10100 + Denormalized number 00100 + Normalized number 00101 + Infinity CR2 CR3 CR4 Unchanged Figure 3-7. Condition Register (CR) MPC561/MPC563 Reference Manual, Rev. 1.2 — — LSB 31 CR5 CR6 CR7 Freescale Semiconductor ...

Page 161

... When a specified CR field is set by a compare instruction, the bits of the specified field are interpreted as shown in Table 3-9. A condition register field can also be accessed by the mfcr, mcrf, and mtcrf instructions. Freescale Semiconductor Table 3-7. If any portion of the result (the 32-bit value placed Table 3-7. Bit Settings for CR0 Field of CR Description Section 3.7.3, “ ...

Page 162

... The OV bit is not altered by compare instructions or other instructions that cannot overflow. 3-18 Description — 00_0000_0000_0000_0000_0 SPR 1 Table 3-10, are based on the operation of an instruction considered Description MPC561/MPC563 Reference Manual, Rev. 1.2 LSB 31 BYTES Unchanged Freescale Semiconductor ...

Page 163

... BO field. If the value in CTR is 0 before being decremented –1 afterward. The count register provides the branch target address for the branch conditional to count register (bcctrx) instructio MSB Field Reset Addr Freescale Semiconductor Description Branch Address Unchanged SPR 8 Figure 3-9. Link Register (LR Loop Count Unchanged SPR 9 Figure 3-10 ...

Page 164

... Power management disabled (normal operation mode) 1 Power management enabled (reduced power mode) 3- — 0000_0000_0000_0000 FE0 SE BE FE1 — IP 0000_0 ID1 Figure 3-11. Machine State Register (MSR) Description MPC561/MPC563 Reference Manual, Rev. 1 POW — DCMPEN 000 X Section 7.5.2, “Hard Freescale Semiconductor 15 0 ILE LSB ...

Page 165

... IR Instruction relocation. 0 Instruction address translation is off; the BBC IMPU does not check for address permission attributes. 1 Instruction address translation is on; the BBC IMPU checks for address permission attributes. Freescale Semiconductor Description Table 3-12.) Table 3-12). MPC561/MPC563 Reference Manual, Rev. 1.2 Central Processing Unit Section 6.1.4, “ ...

Page 166

... For more information about bit settings, see Section 3.15.4.6, “Alignment Exception Data Protection Error Exception 3-22 Description Mode DSISR Unchanged SPR 18 Section 3.15.4.2, “Machine Check Exception (0x00600),” and Section 3.15.4.15, “Implementation-Specific (0x1400).” MPC561/MPC563 Reference Manual, Rev. 1.2 Table 3-12. (0x0200),” Freescale Semiconductor LSB 31 ...

Page 167

... The instruction addressed can be determined from the exception type and status bits. 3.9.7 Machine Status Save/Restore Register 1 (SRR1) The machine status save/restore register 1 (SRR1), SPR 27, saves the machine status on exceptions and restores the machine status when an rfi instruction is executed. Freescale Semiconductor Data Address Unchanged SPR 19 Figure 3-13 ...

Page 168

... This register may be used by the operating system as needed. SPRG3 This register may be used by the operating system as needed. 3- SRR1 Undefined SPR SPRG0 SPRG1 SPRG2 SPRG3 Unchanged Table 3-13. Table 3-13. Uses of SPRG0–SPRG3 Description MPC561/MPC563 Reference Manual, Rev. 1.2 LSB 31 LSB 31 Freescale Semiconductor ...

Page 169

... Non-recoverable Interrupt (NRI). Issuing the mtspr instruction with one of these registers as an operand causes the RI and EE bits to be set or cleared as shown in SPR Number A read (mfspr) of any of these locations is treated as an unimplemented instruction, resulting in a software emulation exception. Freescale Semiconductor SPR 287 Description Table 3-2 Table Table 3-15 ...

Page 170

... Floating-point result is not tiny 1 Floating-point result is tiny Software must insert a sync instruction before reading the FPECR. 3- — 0000_0000_0000_0000 — 0000_0000_0000_0000 SPR 1022 Table 3-16. Table 3-16. FPECR Bit Descriptions Description NOTE MPC561/MPC563 Reference Manual, Rev. 1 DNC DNB DNA Freescale Semiconductor 15 LSB 31 TR ...

Page 171

... Branch and trap instructions — Condition register logical instructions • Processor control instructions, which are used for synchronizing memory accesses. — Move to/from SPR instructions — Move to/from MSR Freescale Semiconductor Model” (IMMR)” Model” Support” MPC561/MPC563 Reference Manual, Rev. 1.2 ...

Page 172

... Add Immediate Carrying and Record rD,rA,SIMM Add Immediate Shifted rD,rA Add to Minus One Extended rD,rA Add to Zero Extended rA,rS,rB AND rA,rS,rB AND with Complement rA,rS,UIMM AND Immediate rA,rS,UIMM AND Immediate Shifted target_addr Branch MPC561/MPC563 Reference Manual, Rev. 1.2 Name Freescale Semiconductor ...

Page 173

... Freescale Semiconductor Operand Syntax BO,BI,target_addr Branch Conditional BO,BI Branch Conditional to Count Register BO,BI Branch Conditional to Link Register crfD,L,rA,rB Compare crfD,L,rA,SIMM Compare Immediate ...

Page 174

... Load Floating-Point Single with Update frD,rA,rB Load Floating-Point Single with Update Indexed frD,rA,rB Load Floating-Point Single Indexed rD,d(rA) Load Half-Word Algebraic rD,d(rA) Load Half-Word Algebraic with Update rD,rA,rB Load Half-Word Algebraic with Update Indexed MPC561/MPC563 Reference Manual, Rev. 1.2 Name Freescale Semiconductor ...

Page 175

... Freescale Semiconductor Operand Syntax rD,rA,rB Load Half-Word Algebraic Indexed rD,rA,rB Load Half-Word Byte-Reverse Indexed rD,d(rA) Load Half-Word and Zero rD,d(rA) Load Half-Word and Zero with Update ...

Page 176

... Store Floating-Point Double Indexed frS,rB Store Floating-Point as Integer Word Indexed frS,d(rA) Store Floating-Point Single frS,d(rA) Store Floating-Point Single with Update frS,rB Store Floating-Point Single with Update Indexed frS,r B Store Floating-Point Single Indexed rS,d(rA) Store Half-Word MPC561/MPC563 Reference Manual, Rev. 1.2 Name Freescale Semiconductor ...

Page 177

... XER is enabled. 3.10.2 Recommended Simplified Mnemonics To simplify assembly language coding, a set of alternative mnemonics is provided for some frequently used operations (such as no-op, load immediate, load address, move register, and complement register). Freescale Semiconductor Operand Syntax rS,rA,rB Store Half-Word Byte-Reverse Indexed rS,d(rA) ...

Page 178

... Likewise, exceptions that are asynchronous and precise are recognized when they occur, but are not handled until all instructions currently in the execute stage successfully complete execution and report their results. 3-34 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor ...

Page 179

... DAR and DSISR) may not be recoverable; the processor may be in the process of saving or restoring these registers. To determine whether the machine state is recoverable, the RI (recoverable exception) bit in SRR1 can be read. During exception processing, the RI bit in the MSR is copied to SRR1 and then cleared. The Freescale Semiconductor Table 3-18. Table 3-18. RCPU Exception Classes ...

Page 180

... Section 3.15.4.1, “System Reset Exception and NMI Section 3.15.4.2, “Machine Check Exception Section 3.15.4.3, “Data Storage Exception Section 3.15.4.5, “External Interrupt MPC561/MPC563 Reference Manual, Rev. 1.2 shows the exception vector offset of (ETR).” Section — (0x0100)” (0x0200)” (0x0300)” 1 Instruction Storage (0x0500)” Freescale Semiconductor ...

Page 181

... Instruction Timing The RCPU processor is pipelined. Because the processing of an instruction is broken into a series of stages, an instruction does not require the processor’s full resources. Freescale Semiconductor Section 3.15.4.6, “Alignment Exception Section 3.15.4.7, “Program Exception Section 3.15.4.8, “Floating-Point Unavailable Exception Section 3.15.4.9, “Decrementer Exception Section 3.15.4.10, “ ...

Page 182

... Table 3-20 indicates the latency and blockage for each type of instruction. Latency refers to the interval from the time an instruction begins execution until it produces a result that is available for use Figure 3-19. Basic Instruction Pipeline MPC561/MPC563 Reference Manual, Rev. 1 load store i1 Freescale Semiconductor ...

Page 183

... MPC561/MPC563. Exception to this rule are bits [16:23] of the fixed-point exception cause register (XER) and the reserved bits of the machine state register (MSR), which are set by the source value on write and return the value last set for it on read. Freescale Semiconductor NOTE Precision ...

Page 184

... The core uses the y bit to predict path for pre-fetch. Prediction is only done for not-ready branch conditions. No prediction is done for branches to the link or count register if the target address is not ready. Refer to the RCPU Reference Manual (conditional branch control) for more information. 3-40 Table 3-20 of this manual. MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor ...

Page 185

... Manual (Floating-point Load Instructions). 3.13.9.2 Optional Instructions The only optional instruction implemented by RCPU hardware is store floating-point as integer word indexed (stfiwx). An attempt to execute any other optional instruction causes an implementation dependent software emulation exception. Freescale Semiconductor Table 3-20. ÷ -1, <anything> ÷ cmpi, cmp, cmpli, and cmpl instructions, the L-bit is applicable MPC561/MPC563 Reference Manual, Rev ...

Page 186

... When the operand is ZERO it is converted to the correct signed ZERO in single-precision format. When the operand is between the range of single denormalized and double denormalized it is considered a programming error. The hardware will handle this case as if the operand was single denormalized. 3-42 MPC561/MPC563 Reference Manual, Rev. 1.2 Freescale Semiconductor ...

Page 187

... Instruction Synchronize (isync) Instruction The isync instruction causes a reflect which waits for all prior instructions to complete and then executes the next sequential instruction. Any instruction after an isync will see all effects of prior instructions. Freescale Semiconductor ≠ ≤ 0) AND (frS[1:11] 896) MPC561/MPC563 Reference Manual, Rev ...

Page 188

... DBAT0U, DBAT0L, DBAT1U, DBAT1L, DBAT2L, DBAT3U, DBAT3L. • Added Registers — For a list of added special purpose registers, refer to 3-44 Chapter 6, “System Configuration and Control.” Mode FE0 MPC561/MPC563 Reference Manual, Rev. 1.2 Protection,” Table 3-21. FE1 Table 3-2, and Table 3-3. Freescale Semiconductor ...

Page 189

... COUNTB[16:31] A non-maskable interrupt (NMI) occurs when the IRQ0 is asserted and the following registers are set. Table 3-23. Register Settings following an NMI Register Name Save/Restore Register 0 (SRR0) Save/Restore Register 1 (SRR1) Freescale Semiconductor Table 3-19. Table 3-22. Table 3-22. Settings Caused by Reset Setting IP depends on internal data bus configuration word ...

Page 190

... A data error was detected. • A storage protection violation was detected by chip-select logic. 3-46 Bits IP No change ME No change LE Bit is copied from ILE DCMPEN This bit is set according to (BBCMCR[EN_COMP] AND BBCMCR[EXC_COMP]) Other Cleared to 0 MPC561/MPC563 Reference Manual, Rev. 1.2 Description Freescale Semiconductor ...

Page 191

... The register settings for machine check exceptions are shown in Table 3-25. Register Settings following a Machine Check Exception Register Name Save/Restore Register 0 (SRR0) Save/Restore Register 1 (SRR1) Freescale Semiconductor Table 3-24 CHSTPE MCIE Action Performed when Exception Detected X ...

Page 192

... Set to bits [21:24] of the instruction if X-form and to bits [1:4] if D-form 22:31 Set to bits [6:15] of the instruction All Set to the effective address of the data access that caused the interrupt Section 6.1.4, “Enhanced Interrupt MPC561/MPC563 Reference Manual, Rev. 1.2 Description Controller,” Freescale Semiconductor ...

Page 193

... The operand of lwarx or stwcx. is not word-aligned. Alignment exceptions use the SRR0 and SRR1 to save the machine state and the DSISR to determine the source of the exception. The register settings for alignment exceptions are shown in Freescale Semiconductor Chapter 4, “Burst Buffer Controller 2 Bits 1 All Set to the effective address of the instruction that the processor would have attempted to execute next if no interrupt conditions were present ...

Page 194

... Set to bits [11:15] of the instruction (rA). Set to either bits [11:15] of the instruction or to any register number not in the range of registers loaded by a valid form instruction, for lmw, lswi, and lswx instructions. Otherwise undefined. MPC561/MPC563 Reference Manual, Rev. 1.2 Setting Description Freescale Semiconductor ...

Page 195

... Trap — A trap type program exception is generated when any of the conditions specified in a trap instruction is met. The register settings for program exceptions are shown in Freescale Semiconductor NOTE Table MPC561/MPC563 Reference Manual, Rev. 1.2 Central Processing Unit 3-28 ...

Page 196

... DCMPEN This bit is set according to (BBCMCR[EN_COMP] AND BBCMCR[EXC_COMP]) Other Cleared to 0 Bits 1 All Set to the effective address of the instruction that caused the exception. [0:15] Cleared to 0 [16:31] Loaded from MSR[16:31] MPC561/MPC563 Reference Manual, Rev. 1.2 Setting Description Setting Description Freescale Semiconductor ...

Page 197

... The register settings for the decrementer exception are shown in Table 3-30. Register Settings Following a Decrementer Exception Register Save/Restore Register 0 (SRR0) Save/Restore Register 1 (SRR1) Machine State Register (MSR) Freescale Semiconductor Bits IP No change ME No change LE Set to value of ILE bit prior to the exception ...

Page 198

... Set to the effective address of the instruction following the System Call instruction [0:15] Undefined [16:31] Loaded from MSR[16:31 change ME No change LE Set to value of ILE bit prior to the exception DCMPEN This bit is set according to (BBCMCR[EN_COMP] AND BBCMCR[EXC_COMP]) Other Cleared to 0 MPC561/MPC563 Reference Manual, Rev. 1.2 Setting Description Freescale Semiconductor ...

Page 199

... The register settings for floating-point assist exceptions are shown in Table 3-33. Register Settings following Floating-Point Assist Exceptions Register Name Save/Restore Register 0 (SRR0) Freescale Semiconductor Support,” for more information. See Bits 1 All Set to the effective address of the instruction following the ...

Page 200

... Set to the effective address of the instruction that caused the interrupt 1:4 Cleared to 0 10:15 Cleared to 0 Other Loaded from bits [16:31] of MSR. In the current implementation, bit 30 of the SRR1 is never cleared, except by loading a zero value from MSR[RI]. MPC561/MPC563 Reference Manual, Rev. 1.2 Description Description Freescale Semiconductor ...

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