C8051F335-GM Silicon Laboratories Inc, C8051F335-GM Datasheet - Page 83
C8051F335-GM
Manufacturer Part Number
C8051F335-GM
Description
IC 8051 MCU 2KB FLASH 20QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F33xr
Specifications of C8051F335-GM
Program Memory Type
FLASH
Program Memory Size
2KB (2K x 8)
Package / Case
20-QFN
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
17
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
17
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F330DK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
No. Of I/o's
17
Ram Memory Size
768Byte
Cpu Speed
25MHz
No. Of Timers
4
Rohs Compliant
Yes
Data Rom Size
128 B
Height
0.88 mm
Length
4 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Width
4 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1451 - ADAPTER PROGRAM TOOLSTICK F330
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1269
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C8051F330/1/2/3/4/5
EA = 0; // this is a dummy instruction with two-byte opcode.
; in assembly:
CLR EA ; clear EA bit.
CLR EA ; this is a dummy instruction with two-byte opcode.
If an interrupt is posted during the execution phase of a "CLR EA" opcode (or any instruction which clears
the EA bit), and the instruction is followed by a single-cycle instruction, the interrupt may be taken. How-
ever, a read of the EA bit will return a '0' inside the interrupt service routine. When the "CLR EA" opcode is
followed by a multi-cycle instruction, the interrupt will not be taken.
Some interrupt-pending flags are automatically cleared by the hardware when the CPU vectors to the ISR.
However, most are not cleared by the hardware and must be cleared by software before returning from the
ISR. If an interrupt-pending flag remains set after the CPU completes the return-from-interrupt (RETI)
instruction, a new interrupt request will be generated immediately and the CPU will re-enter the ISR after
the completion of the next instruction.
9.3.1. MCU Interrupt Sources and Vectors
The MCUs support 13 interrupt sources. Software can simulate an interrupt by setting any interrupt-pend-
ing flag to logic 1. If interrupts are enabled for the flag, an interrupt request will be generated and the CPU
will vector to the ISR address associated with the interrupt-pending flag. MCU interrupt sources, associ-
ated vector addresses, priority order and control bits are summarized in Table 9.4 on page 88. Refer to the
datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt
conditions for the peripheral and the behavior of its interrupt-pending flag(s).
86
Rev. 1.7
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